Building a Flight Controller for FlightGear Sim on Ultra96

The objective of this project is to implement an attitude controller for the Cessna 172P aircraft on an MPSoC Zynq Ultrascale+ embedded in an Ultra96-V2 evaluation board. To validate the correct operation of the implemented controller, the open-source flight simulator FlightGear is used, which provides the necessary state variables to feed the attitude controller implemented in the programmable logic. This controller computes the appropriate control variables that will be sent back to the flight simulator, closing the loop.

One of the problem that I encountered doing this project is that unfourtunately the Ultra96v2 board does not include an Ethernet PHY, and the Ethernet Expansor for this board were too expensive so I found another solution, that is to connect the FlightGear host to the board using an Ethernet to USB dongle, this devices are very cheap and offers good enough performance for this application. However, the use of this dongle complicates the project because it requires to run Petalinux in the PS or to do a driver to communicate with the device and compile it and run it over baremetal or FreeRTOS.

System architechture

A host computer running an instance of FlightGear is configured to periodically send the aircraft's state vector (attitude): pitch, roll, and slip angle. This state vector is sent via a UDP packet through the network interface of the host, which is connected via Ethernet cable to the USB-Ethernet dongle connected to the Ultra96-V2. On the Ultra96-V2, a socket is opened to receive this state vector and subsequently send it to the PL via AXI DMA IP, where the control signal will be calculated using three PID controllers corresponding to each of the attitude axes to be controlled. Once the control vector is calculated, it is first sent through the AXI DMA IP to the PS, where a UDP packet will be created and sent back to the host.

To set the reference variables for our aircraft to follow, an additional communication channel will be established from the host to the PS, which will modify the reference variables via AXI Lite. Consequently, the IP Core developed to calculate the control vector comprises three interfaces: two AXI Stream interfaces (one master and one slave) and one AXI Lite interface, as illustrated in the following image.

Additionally, the data type used for the PID calculations must be considered. For simplicity in development, a fixed-point data type has been chosen. Since FlightGear does not support configuring the output/input in this data format, a converter must also be implemented to transform floating-point data to fixed-point and vice versa.