A. Base Platform and ZYNQMP common image for ZCU102
B. Building the Hardware Overlay
C. Booting the ZCU102
D. Compiling the Resnet50 Model as of DPU Architecture
E. Running the Demo
F. Debug Points or Hints on Vitis DPU TRD with ZCU102 or Custom Board
G. Common issues and solutions from Xilinx Forum and Git-Issues
H. Conclusion

LogicTronix [FPGA Design + Machine Learning Company]

Published March 27, 2023 © GPL3+

ZCU102-Vitis DPU TRD - Vitis AI (3.0)

This Vitis Flow tutorial is expanded tutorial on "Vitis DPU TRD" for ZCU102 with detail steps, Build and BOOT LOG and Debug hints.

IntermediateFull instructions provided4 hours4,521

Things used in this project

Hardware components

Zynq UltraScale+ MPSoC ZCU102

Software apps and online services

AMD Vitis Unified Software Platform

Story

Previously we have few tutorials on "DPU-TRD with VIVADO flow" for different boards, this time we have created "Vitis flow" based "DPU-TRD tutorial for ZCU102". This tutorial is expanded version of tutorial from Github-Vitis-AI-DPU, where you can get DPUCZDX8G_VAI_v3.0/prj/Vitis/README.md. We mainly have customized the DPU architecture (lowest DPU, B512 for building/generating hardware design faster) and we also have re-compiled resnet50.xmodel with Vitis AI tool for B512 DPU in this tutorial.

We are going to use Vitis AI 3.0 (DPU IP v4.1), Vitis Tool 2022.2, XRT 2022.2 in this tutorial. Here are the steps of this tutorial:

A. Base Platform and ZYNQMP common image for ZCU102

In this step

i. Copy the ZCU102 base platform from the Vitis Installation directory, or you can clone the base bsp link and build it locally.

You can find the base platform for ZCU102 and ZCU104 here in your Vitis installation directory: <Vitis_Installation_Directory>/Vitis/2022.2/base_platforms/
Or we also have provided the base platform on download link mentioned at top. This provided one is also copied base platform from Vitis Installation in Zip format.
Creating Base Platform yourself:the base platform can also be created for custom board or ZCU102 by following here: Vitis Platform Creation ZCU104 or KV260 [Link]. For ZCU102 the steps mentioned for Platform creation for ZCU104 matches. For KV260 some of the final steps are different else KV260 also have most steps common with ZCU104.

ii. Download the ZYNQMP common image from Petalinux Web Page [Link]. This common image can be used for any MPSoC Boards, Xilinx Boards or other vendors board or custom carrier board. If you have followed above "Custom Platform Creation Tutorial" then you will have to have create the “ZYNQMP common image” file yourself which you can use on following steps.

B. Building the Hardware Overlay

Here we are going to change the DPU Architecture to B512, the default Vitis-DPU-TRD architecture if B4096 for ZCU102.

Changed the DPU Architecture into B512 in DPUCZDX8G_VAI_v3.0/prj/Vitis/dpu_conf.vh

While changing the DPU architecture we will have to “Compile the resnet50” in Vitis AI tool ourself using the arch.json generated by this step.

The steps going to follow here are:

i. Source Vitis and XRT,

ii. Export ZCU102 Base platform,

iii. Export ZYNQMP common image,

iv. Run the make command, here we will make the DPU only (no SoftMax, for faster building the hardware overlay).

Here is firstpartofBuild LOG [complete Build LOG is attached at footer section]:

Vitis Hardware Development- Build LOG (sourcing and exporting part)

At the end of this Step, we will get the SD_IMG for ZCU102, which we will burn on SD card using the Balena Etcher tool.

Created sd_card.img at binary_container_1 directory

C. Booting the ZCU102

First, burn the SD card with sd_card.img using Balena Etcher. After burning you will see "boot" and "root" partition on SD card. We are going to copy few files into BOOT partition on following steps.

The steps we are going to perform after SD burning are here:

i. Zip the samples directory from DPUCZDX8G_VAI_v3.0/app/samples, this folder has multiple symbolic link. So we are going to copy samples.zip into “ZCU102’s BOOT partition”. So compress:

DPUCZDX8G_VAI_v3.0/app/samples as samples.zip or similar.

ii. Also zip the models from DPUCZDX8G_VAI_v3.0/app/models and copy the zip into “BOOT partition” on ZCU102-SD-Image card.

iii. Also copy “dpu_sw_optimize.tar.gz” to BOOT partition, this will be used for “resizing the root partition memory”.

iv. Now setup the ZCU102 on SD Boot mode, you can change the SW6 for selection of SD Boot mode. For Rev 1.0 board: SW6[4:1] - **off, off, off, on**

v. Plug the SD Card on ZCU102, setup power connection, UART connection. On PC, you can connect UART connection to terminal program like GTKterm, Teraterm, Putty or any. Setup the UART in 115200 baud rate, ZCU102 will give you 4 UART ports, you can connect Serial Port number 18 or check other's to.

vi. Now power on the Board, you will start getting UART messages on your terminal.

vii. Now, at first you can copy the dpu_sw_optimize.tar.gz file we have at BOOT partition in to Home directory on the ZCU102. After copying you can extract it in home partition.

Copying the dpu_sw_optimize.tar.gz and extracting those

Example command (our BOOT partition is accessible at /run/media/mmcblk0p1):

cp -r /run/media/mmcblk0p1/dpu_sw_optimize.tar.gz ~

viii. You can run the bash script inside “dpu_sw_optimize”, that script will resize our partition.

ix. Now you can copy other files to Home directory and extract those.

x. Here we have resnet50.xmodel extracted from "models.zip", this xmodel is default model for DPU B4096.

This boot is general boot which we have ran to see the boot flow and test the default “resnet50.xmodel”. Even though our DPU architecture is changed to two core B512, the default “resnet50.xmodel” based run must give us “fingerprint error” or “fingerprint mismatch” error. Lets see following test:

Test 1: Xmodel not found

Here we are running the default example command with default resnet50.xmodel,

root@zynqmp-common-20222:~# env LD_LIBRARY_PATH=samples/lib XLNX_VART_FIRMWARE=/run/media/mmcblk0p1/dpu.xclbin samples/bin/resnet50 img/bellpeppe-994958.JPEG
WARNING: Logging before InitGoogleLogging() is written to STDERR
F1119 17:23:20.634860 644 serialize_v2.cpp:705] [UNILOG][FATAL][XIR_READ_PB_FAILURE][failed to read pb file] file = resnet50.xmodel
*** Check failure stack trace: ***
Aborted

This error is "file not found error", it is due to our model was not at the home directory. While you copy the resnet50.xmodel in home directory, you will not face this error.

Test 2: fingerprint mismatched

This is important error, as it tells us “dpu is working” but model’s fingerprint is not matched. This error is also expected error, cause we have changed the DPU architecture to B512, while default was B4096.

root@zynqmp-common-20222:~# cp /run/media/mmcblk0p1/app/model/resnet50.xmodel ~
root@zynqmp-common-20222:~# ls
dpu_sw_optimize dpu_sw_optimize.tar.gz img model resnet50.xmodel samples samples.zip
root@zynqmp-common-20222:~#
root@zynqmp-common-20222:~# env LD_LIBRARY_PATH=samples/lib XLNX_VART_FIRMWARE=/run/media/mmcblk0p1/dpu.xclbin samples/bin/resnet50 img/bellpeppe-994958.JPEG
WARNING: Logging before InitGoogleLogging() is written to STDERR
W1119 17:26:32.613843 659 dpu_runner_base_imp.cpp:733] CHECK fingerprint fail! model_fingerprint 0x101000056010407 is un-matched with actual dpu_fingerprint 0x101000056010200. Please re-compile xmodel with dpu_fingerprint 0x101000056010200 and try again.
F1119 17:26:32.614053 659 dpu_runner_base_imp.cpp:695] fingerprint check failure.
*** Check failure stack trace: ***
Aborted
root@zynqmp-common-20222:~#

Now we have to go for “re-compiling” resnet50 model from Model Zoo in Vitis AI 3.0 GPU or CPU tool.

D. Compiling the Resnet50 Model as of DPU Architecture

Now we are going to "Vitis AI 3.0" tool for “re-compiling” the resnet50 model from Model zoo:

i. First download the resnet50 model from Model zoo, there are multiple resnet50 models in Model zoo. We have to find the matching version of resnet50 model based on the input height x width of the image model takes.

We have downloaded the tensorflow version of resnet50, there is also pytorch version of resnet50 models which can also be used. Since Vitis AI 2.5, caffe/darknet models are not supported so there is tensorflow(v1 and v2) and pytorch models only at Vitis AI 3.0 Model Zoo.
Here is the model link, we have used: https://github.com/Xilinx/Vitis-AI/tree/master/model_zoo/model-list/tf_resnetv1_50_imagenet_224_224_6.97G_3.0, there are 3 different tf_resnetv1_50 models at model zoo, we have downloaded un-pruned version while other two are pruned in different scale.

ii. Now we have copied the our DPU fingerprint in arch.json, we can also copy the arch.json from the “binary_container_1/sd_card” directory which is from “Step B”.

arch.json at binary_container_1/sd_card directory

Our DPU Architecture’s fingerprint is (for B512 DPU architecture, Vitis AI 3.0):

{"fingerprint":"0x101000056010200"}

Note: we can also compile resnet50 and some generic model in older Vitis AI CPU or GPU version to. DPU architecture on this tutorial is B512 and of Vitis AI 3.0 version or DPU IP Version 4.1, this version has some new features since Vitis AI 2.5.

For this tutorial with resnet50 network, Vitis AI 2.5 tool version can also support our DPU architecture (fingerprint from Vitis AI 3.0 for DPU IP version 4.1). For testing, we also used Vitis AI 1.4 which did not recognize the DPU fingerprint as few new layer and features are available on DPU IP after the Vitis AI 2.5. We already have installed Vitis AI 2.5 tool, so we are following it, else we will use Vitis AI 3.0.

So, we are compiling our resnet50 tensorflow model with Vitis AI 2.5 (which will be compatible to Vitis AI 3.0 compilation and supported by our SD_Image).

Vitis AI Tool Model compilation

The compilation command for our model compilation is:

vai_c_tensorflow --arch ./arch_zcu102_2xb512_march2023.json -f quantized/quantized_baseline_6.96B_919.pb --output_dir compile_result_zcu102 -n tf_resnet50

After compilation, we will get the compiled Xmodel, we can now rename the tf_resnet50.xmodel as resnet50.xmodel.

Now lets again copy the resnet50.xmodel into ZCU102’s BOOT partition.

E. Running the Demo

As we already have bring up the ZCU102 in “Step C”. Now lets plug the SD card (with BOOT Partition including newly compiled resnet50.xmodel) in ZCU102.

Power on the board and now you can see the UART messages as in previous Step C. After boot completes, lets follow these steps:

i. First enter “ls” on current directory

ii. Now copy the “resnet50.xmodel” from BOOT partition into the home directory

iii. Now lunch the command for running the application, following UART log or screenshot shows the test of resnet50 with different images:

Renset50 model test on ZCU102 (with Vitis AI 3.0 DPU TRD)

F. Debug Points or Hints on Vitis DPU TRD with ZCU102 or Custom Board

In VIVADO flow of DPU TRD we can do "show_dpu", "xdputil query", we can check device tree files and also BOOT log for either DPU working properly or not.

But, in Vitis Flow of DPU-TRD, it is little tricky to debug the design.

For debugging Vitis-DPU-TRDyou can follow:

i. Launch the Application after the boot, if it gives error like:

Fingerprint Error: this error tells DPU is working but model is not matching as DPU architecture. Model can be recompiled for solving this error.
Xmodel error: If xmodel is not there at directory or not accessible then this error may occur. You can recheck xmodel or run with sudo.
DPU Error: If terminal message says DPU error while running the application then

ii. Lsmod command

Lsmod can give the running or active nodes like Zocl, Mali, DMAproxy, UIO etc. This can help us for either Zocl available on the boot or not.

We have included the complete BOOT.LOG along with lsmod message-log in footer of this tutorial.

iii. Dmesg command

Dmesg can give the detail Kernel level log, so if there is any error on hardware level or software level then we can get that in Dmesg LOG. Previously we also saw "dpuczdx8g failed with error" type of messages in Dmesg, this type of error or messages can help us for debugging the hardware designs and solve those.

[ 2.387117] ####### Dpu Loaded Successful ########
[ 2.387130] xlnx-dpu 8f00000001000000.dpuczdx8g: invalid resource
[ 2.387142] xlnx-dpu: probe of 8f00000001000000.dpuczdx8g failed with error -12

iv. If your "dpu" not working on this step, then you have to check "Vitis Base Platform":

Sometime, small thing missed on Step 1( Vitis_Platform_Creation/02-Edge-AI-ZCU104/step1.md) can lead issue on DPU integration. Some of common things to recheck on Vitis PlatformProject are: "Change Clock ID to 1, 2 and 3", "interrupt config", "Enable AXI Slave interfaces from PS to allow kernels access DDR memory" etc on Platform setup.

G. Common issues and solutions from Xilinx Forum and Git-Issues

You can also check Xilinx Vitis AI & AI forum and "Vitis AI-Github Issues" for any issues on Vitis-DPU-TRD for ZCU102. At both platform there are number of questions and best possible solution for different issues for "Vitis DPU TRD" for different MPSoC Boards.

H. Conclusion

This tutorial can be helpful while creating Vitis-DPU-TRD for custom board. For custom board, we have to first create the "Vitis Base Platform", so we can use that platform for building the hardware(DPU) overlay.

Thanks for going through this tutorial!

The Build Log, BOOT Log and Vitis AI log are attached below!

(base) userpc@userPC-3476:/media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis$ source /opt/xilinx/xrt/setup.sh 
XILINX_XRT        : /opt/xilinx/xrt
PATH              : /opt/xilinx/xrt/bin:/home/userpc/anaconda3/bin:/home/userpc/anaconda3/condabin:/home/userpc/bin:/home/userpc/.local/bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/usr/local/games:/snap/bin
LD_LIBRARY_PATH   : /opt/xilinx/xrt/lib:
PYTHONPATH        : /opt/xilinx/xrt/python:
(base) userpc@userPC-3476:/media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis$ source /media/userpc/Storage_Dataset/opt5_2022/Vitis/2022.2/settings64.sh
(base) userpc@userPC-3476:/media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis$ export EDGE_COMMON_SW=/media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/xilinx-zynqmp-common-v2022.2_10141622
(base) userpc@userPC-3476:/media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis$ export SDX_PLATFORM=/media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/xilinx_zcu102_base_202220_1/xilinx_zcu102_base_202220_1.xpfm
(base) userpc@userPC-3476:/media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis$ make all KERNEL=DPU DEVICE=zcu102
/media/userpc/Storage_Dataset/opt5_2022/Vivado/2022.2/bin/vivado -mode batch -source /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/scripts/gen_dpu_xo.tcl -notrace -tclargs binary_container_1/dpu.xo DPUCZDX8G hw zcu102

****** Vivado v2022.2 (64-bit)
  **** SW Build 3671981 on Fri Oct 14 04:59:54 MDT 2022
  **** IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.

WARNING: [Runs 36-547] User Strategy 'Performance_Explore' from file '/home/userpc/.Xilinx/Vivado/2020.2/strategies/Performance_Explore.Vivado Implementation 2020.psg' discarded because strategy with same name already parsed from '/media/userpc/Storage_Dataset/opt5_2022/Vivado/2022.2/strategies/VDI2020.psg'
WARNING: [Runs 36-547] User Strategy 'Performance_Explore' from file '/home/userpc/.Xilinx/Vivado/2020.2/strategies/Performance_Explore_2.Vivado Implementation 2020.psg' discarded because strategy with same name already parsed from '/media/userpc/Storage_Dataset/opt5_2022/Vivado/2022.2/strategies/VDI2020.psg'
WARNING: [Runs 36-547] User Strategy 'Performance_Explore' from file '/home/userpc/.Xilinx/Vivado/2020.2/strategies/Performance_Explore_7.Vivado Implementation 2020.psg' discarded because strategy with same name already parsed from '/media/userpc/Storage_Dataset/opt5_2022/Vivado/2022.2/strategies/VDI2020.psg'
WARNING: [Runs 36-547] User Strategy 'Performance_Explore' from file '/home/userpc/.Xilinx/Vivado/2020.2/strategies/Performance_Explore_5.Vivado Implementation 2020.psg' discarded because strategy with same name already parsed from '/media/userpc/Storage_Dataset/opt5_2022/Vivado/2022.2/strategies/VDI2020.psg'
WARNING: [Runs 36-547] User Strategy 'Performance_Explore' from file '/home/userpc/.Xilinx/Vivado/2020.2/strategies/Performance_Explore_6.Vivado Implementation 2020.psg' discarded because strategy with same name already parsed from '/media/userpc/Storage_Dataset/opt5_2022/Vivado/2022.2/strategies/VDI2020.psg'
WARNING: [Runs 36-547] User Strategy 'Performance_Explore' from file '/home/userpc/.Xilinx/Vivado/2020.2/strategies/Performance_Explore_4.Vivado Implementation 2020.psg' discarded because strategy with same name already parsed from '/media/userpc/Storage_Dataset/opt5_2022/Vivado/2022.2/strategies/VDI2020.psg'
WARNING: [Runs 36-547] User Strategy 'Performance_Explore' from file '/home/userpc/.Xilinx/Vivado/2020.2/strategies/Performance_Explore_3.Vivado Implementation 2020.psg' discarded because strategy with same name already parsed from '/media/userpc/Storage_Dataset/opt5_2022/Vivado/2022.2/strategies/VDI2020.psg'
source /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/scripts/gen_dpu_xo.tcl -notrace
binary_container_1/dpu.xo
create_project: Time (s): cpu = 00:00:06 ; elapsed = 00:00:09 . Memory (MB): peak = 1299.176 ; gain = 2.016 ; free physical = 10477 ; free virtual = 16443
INFO: [IP_Flow 19-5654] Module 'DPUCZDX8G' uses SystemVerilog sources with a Verilog top file. These SystemVerilog files will not be analysed by the packager.
INFO: [IP_Flow 19-1842] HDL Parser: Found include file "src/arch_def.vh" from the top-level HDL file.
INFO: [IP_Flow 19-1842] HDL Parser: Found include file "/media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/dpu_conf.vh" from the top-level HDL file.
INFO: [IP_Flow 19-1841] HDL Parser: Add include file "/media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/dpu_conf.vh" to file group xilinx_anylanguagesynthesis.
INFO: [IP_Flow 19-1841] HDL Parser: Add include file "/media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/dpu_conf.vh" to file group xilinx_anylanguagebehavioralsimulation.
INFO: [IP_Flow 19-1842] HDL Parser: Found include file "src/arch_para.vh" from the top-level HDL file.
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/media/userpc/Storage_Dataset/opt5_2022/Vivado/2022.2/data/ip'.
INFO: [IP_Flow 19-5107] Inferred bus interface 'aclk' of definition 'xilinx.com:signal:clock:1.0' (from X_INTERFACE_INFO parameter from HDL file).
INFO: [IP_Flow 19-5107] Inferred bus interface 'aclk' of definition 'xilinx.com:signal:clock:1.0' (from 'X_INTERFACE_INFO' attribute).
INFO: [IP_Flow 19-5107] Inferred bus interface 'ap_clk_2' of definition 'xilinx.com:signal:clock:1.0' (from X_INTERFACE_INFO parameter from HDL file).
INFO: [IP_Flow 19-5107] Inferred bus interface 'ap_clk_2' of definition 'xilinx.com:signal:clock:1.0' (from 'X_INTERFACE_INFO' attribute).
INFO: [IP_Flow 19-5107] Inferred bus interface 'ap_rst_n_2' of definition 'xilinx.com:signal:reset:1.0' (from X_INTERFACE_INFO parameter from HDL file).
INFO: [IP_Flow 19-5107] Inferred bus interface 'ap_rst_n_2' of definition 'xilinx.com:signal:reset:1.0' (from 'X_INTERFACE_INFO' attribute).
INFO: [IP_Flow 19-5107] Inferred bus interface 'aresetn' of definition 'xilinx.com:signal:reset:1.0' (from X_INTERFACE_INFO parameter from HDL file).
INFO: [IP_Flow 19-5107] Inferred bus interface 'aresetn' of definition 'xilinx.com:signal:reset:1.0' (from 'X_INTERFACE_INFO' attribute).
INFO: [IP_Flow 19-5107] Inferred bus interface 'M_AXI_GP0' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'M_AXI_HP0' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'M_AXI_HP2' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'S_AXI_CONTROL' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'interrupt' of definition 'xilinx.com:signal:interrupt:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-4728] Bus Interface 'interrupt': Added interface parameter 'SENSITIVITY' with value 'LEVEL_HIGH'.
INFO: [IP_Flow 19-4728] Bus Interface 'aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'M_AXI_GP0'.
INFO: [IP_Flow 19-4728] Bus Interface 'aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'aresetn'.
INFO: [IP_Flow 19-4728] Bus Interface 'ap_clk_2': Added interface parameter 'ASSOCIATED_RESET' with value 'ap_rst_n_2'.
INFO: [IP_Flow 19-4728] Bus Interface 'ap_rst_n_2': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
INFO: [IP_Flow 19-4728] Bus Interface 'aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
WARNING: [IP_Flow 19-5661] Bus Interface 'ap_clk_2' does not have any bus interfaces associated with it.
WARNING: [IP_Flow 19-3157] Bus Interface 'ap_rst_n_2': Bus parameter POLARITY is ACTIVE_LOW but port 'ap_rst_n_2' is not *resetn - please double check the POLARITY setting.
WARNING: [IP_Flow 19-731] File Group 'xilinx_anylanguagesynthesis (Synthesis)': "/media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/dpu_conf.vh" file path is not relative to the IP root directory.
WARNING: [IP_Flow 19-4816] The Synthesis file group has two include files that have the same base name. It is not guaranteed which of these two files will be picked up during synthesis/simulation:   src/dpu_conf.vh
  /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/dpu_conf.vh
WARNING: [IP_Flow 19-991] Unrecognized or unsupported file 'src/fingerprint_json.ttcl' found in file group 'Synthesis'.
Resolution: Remove the file from the specified file group.
WARNING: [IP_Flow 19-731] File Group 'xilinx_anylanguagebehavioralsimulation (Simulation)': "/media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/dpu_conf.vh" file path is not relative to the IP root directory.
WARNING: [IP_Flow 19-4816] The Simulation file group has two include files that have the same base name. It is not guaranteed which of these two files will be picked up during synthesis/simulation:   src/dpu_conf.vh
  /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/dpu_conf.vh
WARNING: [IP_Flow 19-991] Unrecognized or unsupported file 'src/fingerprint_json.ttcl' found in file group 'Simulation'.
Resolution: Remove the file from the specified file group.
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
INFO: [IP_Flow 19-795] Syncing license key meta-data
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/media/userpc/Storage_Dataset/opt5_2022/Vivado/2022.2/data/ip'.
INFO: [IP_Flow 19-5107] Inferred bus interface 'ap_clk_2' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument).
INFO: [IP_Flow 19-5107] Inferred bus interface 'ap_rst_n_2' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument).
WARNING: [Vivado 12-4404] The CPU emulation flow in v++ is only supported when using a packaged XO file that contains C-model files, none were found.
INFO: [Common 17-206] Exiting Vivado at Fri Mar 24 13:06:05 2023...
v++ -t hw --platform /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/xilinx_zcu102_base_202220_1/xilinx_zcu102_base_202220_1.xpfm --save-temps --config /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/config_file/prj_config --xp param:compiler.userPostSysLinkOverlayTcl=/media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/syslink/strip_interconnects.tcl  -l --temp_dir binary_container_1 --log_dir binary_container_1/logs --remote_ip_cache binary_container_1/ip_cache -o "binary_container_1/binary_container_1.xclbin" binary_container_1/dpu.xo
WARNING: [v++ 60-1600] The option 'xp' was used directly on the command line, where its usage is deprecated. To ensure input line works for supported operating systems or shells, v++ supports specification for some options in a configuration file. As an alternative, please use options 'advanced.*', 'vivado.*' in a configuration file. Use one or more configuration files along with section headers to define key-value pairs for the advanced properties or parameters. Specify a configuration file using '--config'.
INFO: [v++ 82-185] Check out the auto-generated 'sample_link.ini' configuration file. The file shows how to migrate from deprecated command line --xp switches to configuration file directives.
Option Map File Used: '/media/userpc/Storage_Dataset/opt5_2022/Vitis/2022.2/data/vitis/vpp/optMap.xml'

****** v++ v2022.2 (64-bit)
  **** SW Build 3671529 on 2022-10-13-17:52:11
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.

INFO: [v++ 60-1306] Additional information associated with this v++ link can be found at:
	Reports: /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/reports/link
	Log files: /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/logs/link
Running Dispatch Server on port: 44755
INFO: [v++ 60-1548] Creating build summary session with primary output /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/binary_container_1.xclbin.link_summary, at Fri Mar 24 13:06:22 2023
INFO: [v++ 60-1315] Creating rulecheck session with output '/media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/reports/link/v++_link_binary_container_1_guidance.html', at Fri Mar 24 13:06:22 2023
INFO: [v++ 60-895]   Target platform: /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/xilinx_zcu102_base_202220_1/xilinx_zcu102_base_202220_1.xpfm
INFO: [v++ 60-1578]   This platform contains Xilinx Shell Archive '/media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/xilinx_zcu102_base_202220_1/hw/hw.xsa'
INFO: [v++ 60-629] Linking for hardware target
INFO: [v++ 60-423]   Target device: xilinx_zcu102_base_202220_1
INFO: [v++ 60-1332] Run 'run_link' status: Not started
INFO: [v++ 60-1443] [13:06:23] Run run_link: Step system_link: Started
INFO: [v++ 60-1453] Command Line: system_link --xo /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/dpu.xo -keep --config /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/int/syslinkConfig.ini --xpfm /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/xilinx_zcu102_base_202220_1/xilinx_zcu102_base_202220_1.xpfm --target hw --output_dir /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/int --temp_dir /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/sys_link
INFO: [v++ 60-1454] Run Directory: /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/run_link
INFO: [SYSTEM_LINK 82-70] Extracting xo v3 file /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/dpu.xo
INFO: [SYSTEM_LINK 82-53] Creating IP database /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/sys_link/_sysl/.cdb/xd_ip_db.xml
INFO: [SYSTEM_LINK 82-38] [13:06:25] build_xd_ip_db started: /media/userpc/Storage_Dataset/opt5_2022/Vitis/2022.2/bin/build_xd_ip_db -ip_search 0  -sds-pf /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/sys_link/hw.hpfm -clkid 0 -ip /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/sys_link/iprepo/xilinx_com_RTLKernel_DPUCZDX8G_1_0,DPUCZDX8G -o /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/sys_link/_sysl/.cdb/xd_ip_db.xml
INFO: [SYSTEM_LINK 82-37] [13:06:30] build_xd_ip_db finished successfully
Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 443.012 ; gain = 0.000 ; free physical = 10533 ; free virtual = 16581
INFO: [SYSTEM_LINK 82-51] Create system connectivity graph
INFO: [SYSTEM_LINK 82-102] Applying explicit connections to the system connectivity graph: /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/sys_link/cfgraph/cfgen_cfgraph.xml
INFO: [SYSTEM_LINK 82-38] [13:06:31] cfgen started: /media/userpc/Storage_Dataset/opt5_2022/Vitis/2022.2/bin/cfgen  -nk DPUCZDX8G:2 -sp DPUCZDX8G_1.M_AXI_GP0:HPC0 -sp DPUCZDX8G_1.M_AXI_HP0:HP0 -sp DPUCZDX8G_1.M_AXI_HP2:HP1 -sp DPUCZDX8G_2.M_AXI_GP0:HPC0 -sp DPUCZDX8G_2.M_AXI_HP0:HP2 -sp DPUCZDX8G_2.M_AXI_HP2:HP3 -clock.freqHz 300000000:DPUCZDX8G_1.aclk -clock.freqHz 600000000:DPUCZDX8G_1.ap_clk_2 -clock.freqHz 300000000:DPUCZDX8G_2.aclk -clock.freqHz 600000000:DPUCZDX8G_2.ap_clk_2 -dpa_mem_offload false -dmclkid 0 -r /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/sys_link/_sysl/.cdb/xd_ip_db.xml -o /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/sys_link/cfgraph/cfgen_cfgraph.xml
INFO: [CFGEN 83-0] Kernel Specs: 
INFO: [CFGEN 83-0]   kernel: DPUCZDX8G, num: 2  {DPUCZDX8G_1 DPUCZDX8G_2}
INFO: [CFGEN 83-0] Port Specs: 
INFO: [CFGEN 83-0]   kernel: DPUCZDX8G_1, k_port: M_AXI_GP0, sptag: HPC0
INFO: [CFGEN 83-0]   kernel: DPUCZDX8G_1, k_port: M_AXI_HP0, sptag: HP0
INFO: [CFGEN 83-0]   kernel: DPUCZDX8G_1, k_port: M_AXI_HP2, sptag: HP1
INFO: [CFGEN 83-0]   kernel: DPUCZDX8G_2, k_port: M_AXI_GP0, sptag: HPC0
INFO: [CFGEN 83-0]   kernel: DPUCZDX8G_2, k_port: M_AXI_HP0, sptag: HP2
INFO: [CFGEN 83-0]   kernel: DPUCZDX8G_2, k_port: M_AXI_HP2, sptag: HP3
INFO: [SYSTEM_LINK 82-37] [13:06:34] cfgen finished successfully
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 443.012 ; gain = 0.000 ; free physical = 10539 ; free virtual = 16580
INFO: [SYSTEM_LINK 82-52] Create top-level block diagram
INFO: [SYSTEM_LINK 82-38] [13:06:34] cf2bd started: /media/userpc/Storage_Dataset/opt5_2022/Vitis/2022.2/bin/cf2bd  --linux --trace_buffer 1024 --input_file /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/sys_link/cfgraph/cfgen_cfgraph.xml --ip_db /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/sys_link/_sysl/.cdb/xd_ip_db.xml --cf_name dr --working_dir /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/sys_link/_sysl/.xsd --temp_dir /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/sys_link --output_dir /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/int
INFO: [CF2BD 82-31] Launching cf2xd: cf2xd -linux -trace-buffer 1024 -i /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/sys_link/cfgraph/cfgen_cfgraph.xml -r /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/sys_link/_sysl/.cdb/xd_ip_db.xml -o dr.xml
INFO: [CF2BD 82-28] cf2xd finished successfully
INFO: [CF2BD 82-31] Launching cf_xsd: cf_xsd -disable-address-gen -dn dr -dp /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/sys_link/_sysl/.xsd
INFO: [CF2BD 82-28] cf_xsd finished successfully
INFO: [SYSTEM_LINK 82-37] [13:06:38] cf2bd finished successfully
Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 443.012 ; gain = 0.000 ; free physical = 10531 ; free virtual = 16579
INFO: [v++ 60-1441] [13:06:38] Run run_link: Step system_link: Completed
Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 458.008 ; gain = 0.000 ; free physical = 10587 ; free virtual = 16636
INFO: [v++ 60-1443] [13:06:38] Run run_link: Step cf2sw: Started
INFO: [v++ 60-1453] Command Line: cf2sw -sdsl /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/int/sdsl.dat -rtd /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/int/cf2sw.rtd -nofilter /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/int/cf2sw_full.rtd -xclbin /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/int/xclbin_orig.xml -o /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/int/xclbin_orig.1.xml
INFO: [v++ 60-1454] Run Directory: /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/run_link
INFO: [v++ 60-1441] [13:06:42] Run run_link: Step cf2sw: Completed
Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 458.008 ; gain = 0.000 ; free physical = 10581 ; free virtual = 16634
INFO: [v++ 60-1443] [13:06:42] Run run_link: Step rtd2_system_diagram: Started
INFO: [v++ 60-1453] Command Line: rtd2SystemDiagram
INFO: [v++ 60-1454] Run Directory: /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/run_link
INFO: [v++ 60-1441] [13:06:42] Run run_link: Step rtd2_system_diagram: Completed
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.15 . Memory (MB): peak = 458.008 ; gain = 0.000 ; free physical = 10576 ; free virtual = 16626
INFO: [v++ 60-1443] [13:06:42] Run run_link: Step vpl: Started
INFO: [v++ 60-1453] Command Line: vpl -t hw -f /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/xilinx_zcu102_base_202220_1/xilinx_zcu102_base_202220_1.xpfm -s --remote_ip_cache /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/ip_cache --output_dir /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/int --log_dir /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/logs/link --report_dir /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/reports/link --config /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/int/vplConfig.ini -k /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/int/kernel_info.dat --webtalk_flag Vitis --temp_dir /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link --no-info --iprepo /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/int/xo/ip_repo/xilinx_com_RTLKernel_DPUCZDX8G_1_0 --messageDb /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/run_link/vpl.pb /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/int/dr.bd.tcl
INFO: [v++ 60-1454] Run Directory: /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/run_link

****** vpl v2022.2 (64-bit)
  **** SW Build 3671529 on 2022-10-13-17:52:11
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.

INFO: [VPL 60-839] Read in kernel information from file '/media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/int/kernel_info.dat'.
INFO: [VPL 60-423]   Target device: xilinx_zcu102_base_202220_1
INFO: [VPL 60-1032] Extracting hardware platform to /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/vivado/vpl/.local/hw_platform
[13:06:51] Run vpl: Step create_project: Started
Creating Vivado project.
[13:07:04] Run vpl: Step create_project: Completed
[13:07:04] Run vpl: Step create_bd: Started
[13:07:25] Run vpl: Step create_bd: Completed
[13:07:25] Run vpl: Step update_bd: Started
[13:07:26] Run vpl: Step update_bd: Completed
[13:07:26] Run vpl: Step generate_target: Started
[13:08:18] Run vpl: Step generate_target: Completed
[13:08:18] Run vpl: Step config_hw_runs: Started
[13:08:22] Run vpl: Step config_hw_runs: Completed
[13:08:22] Run vpl: Step synth: Started
[13:08:53] Block-level synthesis in progress, 0 of 30 jobs complete, 4 jobs running.
[13:09:24] Block-level synthesis in progress, 0 of 30 jobs complete, 4 jobs running.
[13:09:54] Block-level synthesis in progress, 3 of 30 jobs complete, 1 job running.
[13:10:24] Block-level synthesis in progress, 4 of 30 jobs complete, 4 jobs running.
[13:10:54] Block-level synthesis in progress, 4 of 30 jobs complete, 4 jobs running.
[13:11:24] Block-level synthesis in progress, 8 of 30 jobs complete, 0 jobs running.
[13:11:54] Block-level synthesis in progress, 8 of 30 jobs complete, 4 jobs running.
[13:12:24] Block-level synthesis in progress, 8 of 30 jobs complete, 4 jobs running.
[13:12:54] Block-level synthesis in progress, 10 of 30 jobs complete, 2 jobs running.
[13:13:25] Block-level synthesis in progress, 13 of 30 jobs complete, 4 jobs running.
[13:13:55] Block-level synthesis in progress, 13 of 30 jobs complete, 4 jobs running.
[13:14:25] Block-level synthesis in progress, 14 of 30 jobs complete, 3 jobs running.
[13:14:55] Block-level synthesis in progress, 15 of 30 jobs complete, 4 jobs running.
[13:15:25] Block-level synthesis in progress, 18 of 30 jobs complete, 3 jobs running.
[13:15:55] Block-level synthesis in progress, 19 of 30 jobs complete, 3 jobs running.
[13:16:26] Block-level synthesis in progress, 21 of 30 jobs complete, 3 jobs running.
[13:16:56] Block-level synthesis in progress, 22 of 30 jobs complete, 4 jobs running.
[13:17:26] Block-level synthesis in progress, 25 of 30 jobs complete, 3 jobs running.
[13:17:56] Block-level synthesis in progress, 26 of 30 jobs complete, 3 jobs running.
[13:18:26] Block-level synthesis in progress, 26 of 30 jobs complete, 3 jobs running.
[13:18:57] Block-level synthesis in progress, 27 of 30 jobs complete, 2 jobs running.
[13:19:27] Block-level synthesis in progress, 28 of 30 jobs complete, 1 job running.
[13:19:57] Block-level synthesis in progress, 28 of 30 jobs complete, 1 job running.
[13:20:27] Block-level synthesis in progress, 28 of 30 jobs complete, 1 job running.
[13:20:57] Block-level synthesis in progress, 28 of 30 jobs complete, 1 job running.
[13:21:27] Block-level synthesis in progress, 28 of 30 jobs complete, 1 job running.
[13:21:57] Block-level synthesis in progress, 28 of 30 jobs complete, 1 job running.
[13:22:28] Block-level synthesis in progress, 29 of 30 jobs complete, 0 jobs running.
[13:22:58] Top-level synthesis in progress.
[13:23:28] Top-level synthesis in progress.
[13:23:53] Run vpl: Step synth: Completed
[13:23:53] Run vpl: Step impl: Started
[13:25:55] Finished 2nd of 6 tasks (FPGA linking synthesized kernels to platform). Elapsed time: 00h 19m 11s 

[13:25:55] Starting logic optimization..
[13:25:55] Phase 1 Retarget
[13:26:25] Phase 2 Constant propagation
[13:26:25] Phase 3 Sweep
[13:26:25] Phase 4 BUFG optimization
[13:26:25] Phase 5 Shift Register Optimization
[13:26:25] Phase 6 Post Processing Netlist
[13:26:25] Finished 3rd of 6 tasks (FPGA logic optimization). Elapsed time: 00h 00m 30s 

[13:26:25] Starting logic placement..
[13:26:25] Phase 1 Placer Initialization
[13:26:25] Phase 1.1 Placer Initialization Netlist Sorting
[13:26:25] Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
[13:26:55] Phase 1.3 Build Placer Netlist Model
[13:27:25] Phase 1.4 Constrain Clocks/Macros
[13:27:25] Phase 2 Global Placement
[13:27:25] Phase 2.1 Floorplanning
[13:27:55] Phase 2.1.1 Partition Driven Placement
[13:27:55] Phase 2.1.1.1 PBP: Partition Driven Placement
[13:28:25] Phase 2.1.1.2 PBP: Clock Region Placement
[13:28:25] Phase 2.1.1.3 PBP: Compute Congestion
[13:28:25] Phase 2.1.1.4 PBP: UpdateTiming
[13:28:25] Phase 2.1.1.5 PBP: Add part constraints
[13:28:25] Phase 2.2 Update Timing before SLR Path Opt
[13:28:25] Phase 2.3 Post-Processing in Floorplanning
[13:28:25] Phase 2.4 Global Placement Core
[13:29:56] Phase 2.4.1 UpdateTiming Before Physical Synthesis
[13:29:56] Phase 2.4.2 Physical Synthesis In Placer
[13:30:26] Phase 3 Detail Placement
[13:30:26] Phase 3.1 Commit Multi Column Macros
[13:30:26] Phase 3.2 Commit Most Macros & LUTRAMs
[13:30:57] Phase 3.3 Small Shape DP
[13:30:57] Phase 3.3.1 Small Shape Clustering
[13:30:57] Phase 3.3.2 Flow Legalize Slice Clusters
[13:30:57] Phase 3.3.3 Slice Area Swap
[13:30:57] Phase 3.3.3.1 Slice Area Swap Initial
[13:31:27] Phase 3.4 Re-assign LUT pins
[13:31:27] Phase 3.5 Pipeline Register Optimization
[13:31:27] Phase 4 Post Placement Optimization and Clean-Up
[13:31:27] Phase 4.1 Post Commit Optimization
[13:31:57] Phase 4.1.1 Post Placement Optimization
[13:31:57] Phase 4.1.1.1 BUFG Insertion
[13:31:57] Phase 1 Physical Synthesis Initialization
[13:31:57] Phase 4.1.1.2 Post Placement Timing Optimization
[13:32:27] Phase 4.2 Post Placement Cleanup
[13:32:27] Phase 4.3 Placer Reporting
[13:32:27] Phase 4.3.1 Print Estimated Congestion
[13:32:27] Phase 4.4 Final Placement Cleanup
[13:33:28] Finished 4th of 6 tasks (FPGA logic placement). Elapsed time: 00h 07m 03s 

[13:33:28] Starting logic routing..
[13:33:28] Phase 1 Build RT Design
[13:33:58] Phase 2 Router Initialization
[13:33:58] Phase 2.1 Fix Topology Constraints
[13:33:58] Phase 2.2 Pre Route Cleanup
[13:33:58] Phase 2.3 Global Clock Net Routing
[13:33:58] Phase 2.4 Update Timing
[13:34:59] Phase 3 Initial Routing
[13:34:59] Phase 3.1 Global Routing
[13:34:59] Phase 4 Rip-up And Reroute
[13:34:59] Phase 4.1 Global Iteration 0
[13:45:04] Phase 4.2 Global Iteration 1
[13:45:34] Phase 5 Delay and Skew Optimization
[13:45:34] Phase 5.1 Delay CleanUp
[13:45:34] Phase 5.1.1 Update Timing
[13:45:34] Phase 5.1.2 Update Timing
[13:46:04] Phase 5.2 Clock Skew Optimization
[13:46:04] Phase 6 Post Hold Fix
[13:46:04] Phase 6.1 Hold Fix Iter
[13:46:04] Phase 6.1.1 Update Timing
[13:46:04] Phase 7 Route finalize
[13:46:04] Phase 8 Verifying routed nets
[13:46:04] Phase 9 Depositing Routes
[13:46:35] Phase 10 Resolve XTalk
[13:46:35] Phase 11 Route finalize
[13:46:35] Phase 12 Post Router Timing
[13:46:35] Finished 5th of 6 tasks (FPGA routing). Elapsed time: 00h 13m 06s 

[13:46:35] Starting bitstream generation..
[13:48:05] Creating bitmap...
Check VPL, containing 1 checks, has run: 0 errors
[13:48:31] Run vpl: Step impl: Completed
[13:48:32] Writing bitstream ./vitis_design_wrapper.bit...
[13:48:32] Finished 6th of 6 tasks (FPGA bitstream generation). Elapsed time: 00h 01m 56s 
[13:48:32] Run vpl: FINISHED. Run Status: impl Complete!
INFO: [v++ 60-1441] [13:48:32] Run run_link: Step vpl: Completed
Time (s): cpu = 00:00:17 ; elapsed = 00:41:50 . Memory (MB): peak = 458.008 ; gain = 0.000 ; free physical = 9222 ; free virtual = 15771
INFO: [v++ 60-1443] [13:48:32] Run run_link: Step rtdgen: Started
INFO: [v++ 60-1453] Command Line: rtdgen
INFO: [v++ 60-1454] Run Directory: /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/run_link
INFO: [v++ 60-1453] Command Line: cf2sw -a /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/int/address_map.xml -sdsl /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/int/sdsl.dat -xclbin /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/int/xclbin_orig.xml -rtd /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/int/binary_container_1.rtd -o /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/int/binary_container_1.xml
INFO: [v++ 60-1652] Cf2sw returned exit code: 0
INFO: [v++ 60-1441] [13:48:36] Run run_link: Step rtdgen: Completed
Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 458.008 ; gain = 0.000 ; free physical = 10005 ; free virtual = 16578
INFO: [v++ 60-1443] [13:48:36] Run run_link: Step xclbinutil: Started
INFO: [v++ 60-1453] Command Line: xclbinutil --add-section BITSTREAM:RAW:/media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/int/system.bit --force --target hw --key-value SYS:dfx_enable:false --add-section :JSON:/media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/int/binary_container_1.rtd --add-section CLOCK_FREQ_TOPOLOGY:JSON:/media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/int/binary_container_1_xml.rtd --add-section BUILD_METADATA:JSON:/media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/int/binary_container_1_build.rtd --add-section EMBEDDED_METADATA:RAW:/media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/int/binary_container_1.xml --add-section SYSTEM_METADATA:RAW:/media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/int/systemDiagramModelSlrBaseAddress.json --key-value SYS:PlatformVBNV:xilinx.com_xd_xilinx_zcu102_base_202220_1_202220_1 --output /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/binary_container_1.xclbin
INFO: [v++ 60-1454] Run Directory: /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/run_link
XRT Build Version: 2.8.0 (2020.2)
       Build Date: 2022-10-30 14:58:06
          Hash ID: b94857f15ba8c8251df446e8c51af7e0a7c9e061
Creating a default 'in-memory' xclbin image.

Section: 'BITSTREAM'(0) was successfully added.
Size   : 26510905 bytes
Format : RAW
File   : '/media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/int/system.bit'

Section: 'MEM_TOPOLOGY'(6) was successfully added.
Format : JSON
File   : 'mem_topology'

Section: 'IP_LAYOUT'(8) was successfully added.
Format : JSON
File   : 'ip_layout'

Section: 'CONNECTIVITY'(7) was successfully added.
Format : JSON
File   : 'connectivity'
WARNING: Skipping CLOCK_FREQ_TOPOLOGY section for count size is zero.
WARNING: Section 'CLOCK_FREQ_TOPOLOGY' content is empty.  No data in the given JSON file.

Section: 'CLOCK_FREQ_TOPOLOGY'(11) was empty.  No action taken.
Format : JSON
File   : '/media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/int/binary_container_1_xml.rtd'

Section: 'BUILD_METADATA'(14) was successfully added.
Size   : 4904 bytes
Format : JSON
File   : '/media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/int/binary_container_1_build.rtd'

Section: 'EMBEDDED_METADATA'(2) was successfully added.
Size   : 5287 bytes
Format : RAW
File   : '/media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/int/binary_container_1.xml'

Section: 'SYSTEM_METADATA'(22) was successfully added.
Size   : 31196 bytes
Format : RAW
File   : '/media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/int/systemDiagramModelSlrBaseAddress.json'
Successfully wrote (26566894 bytes) to the output file: /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/binary_container_1.xclbin
Leaving xclbinutil.
INFO: [v++ 60-1441] [13:48:37] Run run_link: Step xclbinutil: Completed
Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.62 . Memory (MB): peak = 458.008 ; gain = 0.000 ; free physical = 9974 ; free virtual = 16578
INFO: [v++ 60-1443] [13:48:37] Run run_link: Step xclbinutilinfo: Started
INFO: [v++ 60-1453] Command Line: xclbinutil --quiet --force --info /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/binary_container_1.xclbin.info --input /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/binary_container_1.xclbin
INFO: [v++ 60-1454] Run Directory: /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/run_link
INFO: [v++ 60-1441] [13:48:37] Run run_link: Step xclbinutilinfo: Completed
Time (s): cpu = 00:00:00.3 ; elapsed = 00:00:00.34 . Memory (MB): peak = 458.008 ; gain = 0.000 ; free physical = 9973 ; free virtual = 16578
INFO: [v++ 60-1443] [13:48:37] Run run_link: Step generate_sc_driver: Started
INFO: [v++ 60-1453] Command Line: 
INFO: [v++ 60-1454] Run Directory: /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/run_link
INFO: [v++ 60-1441] [13:48:37] Run run_link: Step generate_sc_driver: Completed
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 458.008 ; gain = 0.000 ; free physical = 9974 ; free virtual = 16578
Check POST-VPL, containing 1 checks, has run: 0 errors
INFO: [v++ 60-244] Generating system estimate report...
INFO: [v++ 60-1092] Generated system estimate report: /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/reports/link/system_estimate_binary_container_1.xtxt
INFO: [v++ 60-2397] Platform default or user specified output type sd_card detected but is not a supported output for v++ --link. Use the v++ --package option instead to create SD card output.
INFO: [v++ 60-586] Created binary_container_1/binary_container_1.xclbin
INFO: [v++ 60-1307] Run completed. Additional information can be found in:
	Guidance: /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/reports/link/v++_link_binary_container_1_guidance.html
	Timing Report: /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/reports/link/imp/impl_1_vitis_design_wrapper_timing_summary_routed.rpt
	Vivado Log: /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/logs/link/vivado.log
	Steps Log File: /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/logs/link/link.steps.log

INFO: [v++ 60-2343] Use the vitis_analyzer tool to visualize and navigate the relevant reports. Run the following command. 
    vitis_analyzer /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/binary_container_1.xclbin.link_summary 
INFO: [v++ 60-791] Total elapsed time: 0h 42m 25s
INFO: [v++ 60-1653] Closing dispatch client.
v++ -t hw --platform /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/xilinx_zcu102_base_202220_1/xilinx_zcu102_base_202220_1.xpfm -p binary_container_1/binary_container_1.xclbin -o binary_container_1/dpu.xclbin --package.out_dir binary_container_1 --package.rootfs /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/xilinx-zynqmp-common-v2022.2_10141622/rootfs.ext4 --package.sd_file /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/xilinx-zynqmp-common-v2022.2_10141622/Image 
Option Map File Used: '/media/userpc/Storage_Dataset/opt5_2022/Vitis/2022.2/data/vitis/vpp/optMap.xml'

****** v++ v2022.2 (64-bit)
  **** SW Build 3671529 on 2022-10-13-17:52:11
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.

INFO: [v++ 60-1306] Additional information associated with this v++ package can be found at:
	Reports: /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/_x/reports/package
	Log files: /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/_x/logs/package
Running Dispatch Server on port: 44945
INFO: [v++ 60-1548] Creating build summary session with primary output /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/dpu.xclbin.package_summary, at Fri Mar 24 13:48:51 2023
INFO: [v++ 60-1315] Creating rulecheck session with output '/media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/_x/reports/package/v++_package_dpu_guidance.html', at Fri Mar 24 13:48:51 2023
INFO: [v++ 60-895]   Target platform: /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/xilinx_zcu102_base_202220_1/xilinx_zcu102_base_202220_1.xpfm
INFO: [v++ 60-1578]   This platform contains Xilinx Shell Archive '/media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/xilinx_zcu102_base_202220_1/hw/hw.xsa'
INFO: [v++ 60-2256] Packaging for hardware

Section: 'SYSTEM_METADATA'(22) was successfully written.
Format: RAW
File  : '/media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/_x/package/extractedSystemDiagram.json'
ERROR: [v++ 60-2254] File specified by package.rootfs option is not valid: /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/xilinx-zynqmp-common-v2022.2_10141622/rootfs.ext4
ERROR: [v++ 60-702] Failed to finish packaging
INFO: [v++ 60-1653] Closing dispatch client.
Makefile:111: recipe for target 'package' failed
make: *** [package] Error 1
(base) userpc@userPC-3476:/media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis$ make clean
rm -f *.o *.elf *.log *.jou sample* v++* *.xclbin *.xclbin*
rm -rf binary_container_1/ packaged_*/ tmp_*/ .Xil/ _x/
(base) userpc@userPC-3476:/media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis$ export EDGE_COMMON_SW=/media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/xilinx-zynqmp-common-v2022.2_10141622/xilinx-zynqmp-common-v2022.2/
(base) userpc@userPC-3476:/media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis$ make all KERNEL=DPU DEVICE=zcu102
/media/userpc/Storage_Dataset/opt5_2022/Vivado/2022.2/bin/vivado -mode batch -source /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/scripts/gen_dpu_xo.tcl -notrace -tclargs binary_container_1/dpu.xo DPUCZDX8G hw zcu102

****** Vivado v2022.2 (64-bit)
  **** SW Build 3671981 on Fri Oct 14 04:59:54 MDT 2022
  **** IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.

WARNING: [Runs 36-547] User Strategy 'Performance_Explore' from file '/home/userpc/.Xilinx/Vivado/2020.2/strategies/Performance_Explore.Vivado Implementation 2020.psg' discarded because strategy with same name already parsed from '/media/userpc/Storage_Dataset/opt5_2022/Vivado/2022.2/strategies/VDI2020.psg'
WARNING: [Runs 36-547] User Strategy 'Performance_Explore' from file '/home/userpc/.Xilinx/Vivado/2020.2/strategies/Performance_Explore_2.Vivado Implementation 2020.psg' discarded because strategy with same name already parsed from '/media/userpc/Storage_Dataset/opt5_2022/Vivado/2022.2/strategies/VDI2020.psg'
WARNING: [Runs 36-547] User Strategy 'Performance_Explore' from file '/home/userpc/.Xilinx/Vivado/2020.2/strategies/Performance_Explore_7.Vivado Implementation 2020.psg' discarded because strategy with same name already parsed from '/media/userpc/Storage_Dataset/opt5_2022/Vivado/2022.2/strategies/VDI2020.psg'
WARNING: [Runs 36-547] User Strategy 'Performance_Explore' from file '/home/userpc/.Xilinx/Vivado/2020.2/strategies/Performance_Explore_5.Vivado Implementation 2020.psg' discarded because strategy with same name already parsed from '/media/userpc/Storage_Dataset/opt5_2022/Vivado/2022.2/strategies/VDI2020.psg'
WARNING: [Runs 36-547] User Strategy 'Performance_Explore' from file '/home/userpc/.Xilinx/Vivado/2020.2/strategies/Performance_Explore_6.Vivado Implementation 2020.psg' discarded because strategy with same name already parsed from '/media/userpc/Storage_Dataset/opt5_2022/Vivado/2022.2/strategies/VDI2020.psg'
WARNING: [Runs 36-547] User Strategy 'Performance_Explore' from file '/home/userpc/.Xilinx/Vivado/2020.2/strategies/Performance_Explore_4.Vivado Implementation 2020.psg' discarded because strategy with same name already parsed from '/media/userpc/Storage_Dataset/opt5_2022/Vivado/2022.2/strategies/VDI2020.psg'
WARNING: [Runs 36-547] User Strategy 'Performance_Explore' from file '/home/userpc/.Xilinx/Vivado/2020.2/strategies/Performance_Explore_3.Vivado Implementation 2020.psg' discarded because strategy with same name already parsed from '/media/userpc/Storage_Dataset/opt5_2022/Vivado/2022.2/strategies/VDI2020.psg'
source /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/scripts/gen_dpu_xo.tcl -notrace
binary_container_1/dpu.xo
INFO: [IP_Flow 19-5654] Module 'DPUCZDX8G' uses SystemVerilog sources with a Verilog top file. These SystemVerilog files will not be analysed by the packager.
INFO: [IP_Flow 19-1842] HDL Parser: Found include file "src/arch_def.vh" from the top-level HDL file.
INFO: [IP_Flow 19-1842] HDL Parser: Found include file "/media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/dpu_conf.vh" from the top-level HDL file.
INFO: [IP_Flow 19-1841] HDL Parser: Add include file "/media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/dpu_conf.vh" to file group xilinx_anylanguagesynthesis.
INFO: [IP_Flow 19-1841] HDL Parser: Add include file "/media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/dpu_conf.vh" to file group xilinx_anylanguagebehavioralsimulation.
INFO: [IP_Flow 19-1842] HDL Parser: Found include file "src/arch_para.vh" from the top-level HDL file.
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/media/userpc/Storage_Dataset/opt5_2022/Vivado/2022.2/data/ip'.
INFO: [IP_Flow 19-5107] Inferred bus interface 'aclk' of definition 'xilinx.com:signal:clock:1.0' (from X_INTERFACE_INFO parameter from HDL file).
INFO: [IP_Flow 19-5107] Inferred bus interface 'aclk' of definition 'xilinx.com:signal:clock:1.0' (from 'X_INTERFACE_INFO' attribute).
INFO: [IP_Flow 19-5107] Inferred bus interface 'ap_clk_2' of definition 'xilinx.com:signal:clock:1.0' (from X_INTERFACE_INFO parameter from HDL file).
INFO: [IP_Flow 19-5107] Inferred bus interface 'ap_clk_2' of definition 'xilinx.com:signal:clock:1.0' (from 'X_INTERFACE_INFO' attribute).
INFO: [IP_Flow 19-5107] Inferred bus interface 'ap_rst_n_2' of definition 'xilinx.com:signal:reset:1.0' (from X_INTERFACE_INFO parameter from HDL file).
INFO: [IP_Flow 19-5107] Inferred bus interface 'ap_rst_n_2' of definition 'xilinx.com:signal:reset:1.0' (from 'X_INTERFACE_INFO' attribute).
INFO: [IP_Flow 19-5107] Inferred bus interface 'aresetn' of definition 'xilinx.com:signal:reset:1.0' (from X_INTERFACE_INFO parameter from HDL file).
INFO: [IP_Flow 19-5107] Inferred bus interface 'aresetn' of definition 'xilinx.com:signal:reset:1.0' (from 'X_INTERFACE_INFO' attribute).
INFO: [IP_Flow 19-5107] Inferred bus interface 'M_AXI_GP0' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'M_AXI_HP0' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'M_AXI_HP2' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'S_AXI_CONTROL' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'interrupt' of definition 'xilinx.com:signal:interrupt:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-4728] Bus Interface 'interrupt': Added interface parameter 'SENSITIVITY' with value 'LEVEL_HIGH'.
INFO: [IP_Flow 19-4728] Bus Interface 'aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'M_AXI_GP0'.
INFO: [IP_Flow 19-4728] Bus Interface 'aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'aresetn'.
INFO: [IP_Flow 19-4728] Bus Interface 'ap_clk_2': Added interface parameter 'ASSOCIATED_RESET' with value 'ap_rst_n_2'.
INFO: [IP_Flow 19-4728] Bus Interface 'ap_rst_n_2': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
INFO: [IP_Flow 19-4728] Bus Interface 'aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
WARNING: [IP_Flow 19-5661] Bus Interface 'ap_clk_2' does not have any bus interfaces associated with it.
WARNING: [IP_Flow 19-3157] Bus Interface 'ap_rst_n_2': Bus parameter POLARITY is ACTIVE_LOW but port 'ap_rst_n_2' is not *resetn - please double check the POLARITY setting.
WARNING: [IP_Flow 19-731] File Group 'xilinx_anylanguagesynthesis (Synthesis)': "/media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/dpu_conf.vh" file path is not relative to the IP root directory.
WARNING: [IP_Flow 19-4816] The Synthesis file group has two include files that have the same base name. It is not guaranteed which of these two files will be picked up during synthesis/simulation:   src/dpu_conf.vh
  /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/dpu_conf.vh
WARNING: [IP_Flow 19-991] Unrecognized or unsupported file 'src/fingerprint_json.ttcl' found in file group 'Synthesis'.
Resolution: Remove the file from the specified file group.
WARNING: [IP_Flow 19-731] File Group 'xilinx_anylanguagebehavioralsimulation (Simulation)': "/media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/dpu_conf.vh" file path is not relative to the IP root directory.
WARNING: [IP_Flow 19-4816] The Simulation file group has two include files that have the same base name. It is not guaranteed which of these two files will be picked up during synthesis/simulation:   src/dpu_conf.vh
  /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/dpu_conf.vh
WARNING: [IP_Flow 19-991] Unrecognized or unsupported file 'src/fingerprint_json.ttcl' found in file group 'Simulation'.
Resolution: Remove the file from the specified file group.
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
INFO: [IP_Flow 19-795] Syncing license key meta-data
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/media/userpc/Storage_Dataset/opt5_2022/Vivado/2022.2/data/ip'.
INFO: [IP_Flow 19-5107] Inferred bus interface 'ap_clk_2' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument).
INFO: [IP_Flow 19-5107] Inferred bus interface 'ap_rst_n_2' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument).
WARNING: [Vivado 12-4404] The CPU emulation flow in v++ is only supported when using a packaged XO file that contains C-model files, none were found.
INFO: [Common 17-206] Exiting Vivado at Fri Mar 24 13:55:24 2023...
v++ -t hw --platform /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/xilinx_zcu102_base_202220_1/xilinx_zcu102_base_202220_1.xpfm --save-temps --config /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/config_file/prj_config --xp param:compiler.userPostSysLinkOverlayTcl=/media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/syslink/strip_interconnects.tcl  -l --temp_dir binary_container_1 --log_dir binary_container_1/logs --remote_ip_cache binary_container_1/ip_cache -o "binary_container_1/binary_container_1.xclbin" binary_container_1/dpu.xo
WARNING: [v++ 60-1600] The option 'xp' was used directly on the command line, where its usage is deprecated. To ensure input line works for supported operating systems or shells, v++ supports specification for some options in a configuration file. As an alternative, please use options 'advanced.*', 'vivado.*' in a configuration file. Use one or more configuration files along with section headers to define key-value pairs for the advanced properties or parameters. Specify a configuration file using '--config'.
INFO: [v++ 82-185] Check out the auto-generated 'sample_link.ini' configuration file. The file shows how to migrate from deprecated command line --xp switches to configuration file directives.
Option Map File Used: '/media/userpc/Storage_Dataset/opt5_2022/Vitis/2022.2/data/vitis/vpp/optMap.xml'

****** v++ v2022.2 (64-bit)
  **** SW Build 3671529 on 2022-10-13-17:52:11
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.

INFO: [v++ 60-1306] Additional information associated with this v++ link can be found at:
	Reports: /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/reports/link
	Log files: /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/logs/link
Running Dispatch Server on port: 34361
INFO: [v++ 60-1548] Creating build summary session with primary output /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/binary_container_1.xclbin.link_summary, at Fri Mar 24 13:55:39 2023
INFO: [v++ 60-1315] Creating rulecheck session with output '/media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/reports/link/v++_link_binary_container_1_guidance.html', at Fri Mar 24 13:55:39 2023
INFO: [v++ 60-895]   Target platform: /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/xilinx_zcu102_base_202220_1/xilinx_zcu102_base_202220_1.xpfm
INFO: [v++ 60-1578]   This platform contains Xilinx Shell Archive '/media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/xilinx_zcu102_base_202220_1/hw/hw.xsa'
INFO: [v++ 60-629] Linking for hardware target
INFO: [v++ 60-423]   Target device: xilinx_zcu102_base_202220_1
INFO: [v++ 60-1332] Run 'run_link' status: Not started
INFO: [v++ 60-1443] [13:55:40] Run run_link: Step system_link: Started
INFO: [v++ 60-1453] Command Line: system_link --xo /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/dpu.xo -keep --config /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/int/syslinkConfig.ini --xpfm /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/xilinx_zcu102_base_202220_1/xilinx_zcu102_base_202220_1.xpfm --target hw --output_dir /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/int --temp_dir /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/sys_link
INFO: [v++ 60-1454] Run Directory: /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/run_link
INFO: [SYSTEM_LINK 82-70] Extracting xo v3 file /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/dpu.xo
INFO: [SYSTEM_LINK 82-53] Creating IP database /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/sys_link/_sysl/.cdb/xd_ip_db.xml
INFO: [SYSTEM_LINK 82-38] [13:55:42] build_xd_ip_db started: /media/userpc/Storage_Dataset/opt5_2022/Vitis/2022.2/bin/build_xd_ip_db -ip_search 0  -sds-pf /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/sys_link/hw.hpfm -clkid 0 -ip /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/sys_link/iprepo/xilinx_com_RTLKernel_DPUCZDX8G_1_0,DPUCZDX8G -o /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/sys_link/_sysl/.cdb/xd_ip_db.xml
INFO: [SYSTEM_LINK 82-37] [13:55:47] build_xd_ip_db finished successfully
Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 450.203 ; gain = 0.000 ; free physical = 10279 ; free virtual = 16536
INFO: [SYSTEM_LINK 82-51] Create system connectivity graph
INFO: [SYSTEM_LINK 82-102] Applying explicit connections to the system connectivity graph: /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/sys_link/cfgraph/cfgen_cfgraph.xml
INFO: [SYSTEM_LINK 82-38] [13:55:47] cfgen started: /media/userpc/Storage_Dataset/opt5_2022/Vitis/2022.2/bin/cfgen  -nk DPUCZDX8G:2 -sp DPUCZDX8G_1.M_AXI_GP0:HPC0 -sp DPUCZDX8G_1.M_AXI_HP0:HP0 -sp DPUCZDX8G_1.M_AXI_HP2:HP1 -sp DPUCZDX8G_2.M_AXI_GP0:HPC0 -sp DPUCZDX8G_2.M_AXI_HP0:HP2 -sp DPUCZDX8G_2.M_AXI_HP2:HP3 -clock.freqHz 300000000:DPUCZDX8G_1.aclk -clock.freqHz 600000000:DPUCZDX8G_1.ap_clk_2 -clock.freqHz 300000000:DPUCZDX8G_2.aclk -clock.freqHz 600000000:DPUCZDX8G_2.ap_clk_2 -dpa_mem_offload false -dmclkid 0 -r /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/sys_link/_sysl/.cdb/xd_ip_db.xml -o /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/sys_link/cfgraph/cfgen_cfgraph.xml
INFO: [CFGEN 83-0] Kernel Specs: 
INFO: [CFGEN 83-0]   kernel: DPUCZDX8G, num: 2  {DPUCZDX8G_1 DPUCZDX8G_2}
INFO: [CFGEN 83-0] Port Specs: 
INFO: [CFGEN 83-0]   kernel: DPUCZDX8G_1, k_port: M_AXI_GP0, sptag: HPC0
INFO: [CFGEN 83-0]   kernel: DPUCZDX8G_1, k_port: M_AXI_HP0, sptag: HP0
INFO: [CFGEN 83-0]   kernel: DPUCZDX8G_1, k_port: M_AXI_HP2, sptag: HP1
INFO: [CFGEN 83-0]   kernel: DPUCZDX8G_2, k_port: M_AXI_GP0, sptag: HPC0
INFO: [CFGEN 83-0]   kernel: DPUCZDX8G_2, k_port: M_AXI_HP0, sptag: HP2
INFO: [CFGEN 83-0]   kernel: DPUCZDX8G_2, k_port: M_AXI_HP2, sptag: HP3
INFO: [SYSTEM_LINK 82-37] [13:55:50] cfgen finished successfully
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 450.203 ; gain = 0.000 ; free physical = 10276 ; free virtual = 16536
INFO: [SYSTEM_LINK 82-52] Create top-level block diagram
INFO: [SYSTEM_LINK 82-38] [13:55:50] cf2bd started: /media/userpc/Storage_Dataset/opt5_2022/Vitis/2022.2/bin/cf2bd  --linux --trace_buffer 1024 --input_file /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/sys_link/cfgraph/cfgen_cfgraph.xml --ip_db /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/sys_link/_sysl/.cdb/xd_ip_db.xml --cf_name dr --working_dir /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/sys_link/_sysl/.xsd --temp_dir /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/sys_link --output_dir /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/int
INFO: [CF2BD 82-31] Launching cf2xd: cf2xd -linux -trace-buffer 1024 -i /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/sys_link/cfgraph/cfgen_cfgraph.xml -r /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/sys_link/_sysl/.cdb/xd_ip_db.xml -o dr.xml
INFO: [CF2BD 82-28] cf2xd finished successfully
INFO: [CF2BD 82-31] Launching cf_xsd: cf_xsd -disable-address-gen -dn dr -dp /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/sys_link/_sysl/.xsd
INFO: [CF2BD 82-28] cf_xsd finished successfully
INFO: [SYSTEM_LINK 82-37] [13:55:53] cf2bd finished successfully
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 450.203 ; gain = 0.000 ; free physical = 10268 ; free virtual = 16534
INFO: [v++ 60-1441] [13:55:53] Run run_link: Step system_link: Completed
Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 446.852 ; gain = 0.000 ; free physical = 10323 ; free virtual = 16589
INFO: [v++ 60-1443] [13:55:53] Run run_link: Step cf2sw: Started
INFO: [v++ 60-1453] Command Line: cf2sw -sdsl /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/int/sdsl.dat -rtd /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/int/cf2sw.rtd -nofilter /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/int/cf2sw_full.rtd -xclbin /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/int/xclbin_orig.xml -o /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/int/xclbin_orig.1.xml
INFO: [v++ 60-1454] Run Directory: /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/run_link
INFO: [v++ 60-1441] [13:55:57] Run run_link: Step cf2sw: Completed
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 446.852 ; gain = 0.000 ; free physical = 10326 ; free virtual = 16590
INFO: [v++ 60-1443] [13:55:57] Run run_link: Step rtd2_system_diagram: Started
INFO: [v++ 60-1453] Command Line: rtd2SystemDiagram
INFO: [v++ 60-1454] Run Directory: /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/run_link
INFO: [v++ 60-1441] [13:55:57] Run run_link: Step rtd2_system_diagram: Completed
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.15 . Memory (MB): peak = 446.852 ; gain = 0.000 ; free physical = 10316 ; free virtual = 16582
INFO: [v++ 60-1443] [13:55:57] Run run_link: Step vpl: Started
INFO: [v++ 60-1453] Command Line: vpl -t hw -f /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/xilinx_zcu102_base_202220_1/xilinx_zcu102_base_202220_1.xpfm -s --remote_ip_cache /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/ip_cache --output_dir /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/int --log_dir /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/logs/link --report_dir /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/reports/link --config /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/int/vplConfig.ini -k /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/int/kernel_info.dat --webtalk_flag Vitis --temp_dir /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link --no-info --iprepo /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/int/xo/ip_repo/xilinx_com_RTLKernel_DPUCZDX8G_1_0 --messageDb /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/run_link/vpl.pb /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/int/dr.bd.tcl
INFO: [v++ 60-1454] Run Directory: /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/run_link

****** vpl v2022.2 (64-bit)
  **** SW Build 3671529 on 2022-10-13-17:52:11
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.

INFO: [VPL 60-839] Read in kernel information from file '/media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/int/kernel_info.dat'.
INFO: [VPL 60-423]   Target device: xilinx_zcu102_base_202220_1
INFO: [VPL 60-1032] Extracting hardware platform to /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/vivado/vpl/.local/hw_platform
[13:56:06] Run vpl: Step create_project: Started
Creating Vivado project.
[13:56:14] Run vpl: Step create_project: Completed
[13:56:14] Run vpl: Step create_bd: Started
[13:56:26] Run vpl: Step create_bd: Completed
[13:56:26] Run vpl: Step update_bd: Started
[13:56:27] Run vpl: Step update_bd: Completed
[13:56:27] Run vpl: Step generate_target: Started
[13:57:16] Run vpl: Step generate_target: Completed
[13:57:16] Run vpl: Step config_hw_runs: Started
[13:57:19] Run vpl: Step config_hw_runs: Completed
[13:57:19] Run vpl: Step synth: Started
[13:57:50] Block-level synthesis in progress, 0 of 30 jobs complete, 4 jobs running.
[13:58:21] Block-level synthesis in progress, 0 of 30 jobs complete, 4 jobs running.
[13:58:51] Block-level synthesis in progress, 0 of 30 jobs complete, 4 jobs running.
[13:59:22] Block-level synthesis in progress, 4 of 30 jobs complete, 4 jobs running.
[13:59:52] Block-level synthesis in progress, 4 of 30 jobs complete, 4 jobs running.
[14:00:22] Block-level synthesis in progress, 4 of 30 jobs complete, 4 jobs running.
[14:00:52] Block-level synthesis in progress, 8 of 30 jobs complete, 4 jobs running.
[14:01:23] Block-level synthesis in progress, 8 of 30 jobs complete, 4 jobs running.
[14:01:53] Block-level synthesis in progress, 8 of 30 jobs complete, 4 jobs running.
[14:02:23] Block-level synthesis in progress, 13 of 30 jobs complete, 3 jobs running.
[14:02:53] Block-level synthesis in progress, 13 of 30 jobs complete, 4 jobs running.
[14:03:23] Block-level synthesis in progress, 13 of 30 jobs complete, 4 jobs running.
[14:03:53] Block-level synthesis in progress, 15 of 30 jobs complete, 4 jobs running.
[14:04:24] Block-level synthesis in progress, 17 of 30 jobs complete, 2 jobs running.
[14:04:54] Block-level synthesis in progress, 20 of 30 jobs complete, 2 jobs running.
[14:05:24] Block-level synthesis in progress, 22 of 30 jobs complete, 3 jobs running.
[14:05:54] Block-level synthesis in progress, 22 of 30 jobs complete, 4 jobs running.
[14:06:24] Block-level synthesis in progress, 23 of 30 jobs complete, 4 jobs running.
[14:06:55] Block-level synthesis in progress, 23 of 30 jobs complete, 4 jobs running.
[14:07:25] Block-level synthesis in progress, 26 of 30 jobs complete, 3 jobs running.
[14:07:55] Block-level synthesis in progress, 27 of 30 jobs complete, 2 jobs running.
[14:08:25] Block-level synthesis in progress, 27 of 30 jobs complete, 2 jobs running.
[14:08:55] Block-level synthesis in progress, 28 of 30 jobs complete, 1 job running.
[14:09:25] Block-level synthesis in progress, 28 of 30 jobs complete, 1 job running.
[14:09:56] Block-level synthesis in progress, 28 of 30 jobs complete, 1 job running.
[14:10:26] Block-level synthesis in progress, 28 of 30 jobs complete, 1 job running.
[14:10:56] Block-level synthesis in progress, 29 of 30 jobs complete, 0 jobs running.
[14:11:26] Top-level synthesis in progress.
[14:11:56] Top-level synthesis in progress.
[14:12:13] Run vpl: Step synth: Completed
[14:12:13] Run vpl: Step impl: Started
[14:14:14] Finished 2nd of 6 tasks (FPGA linking synthesized kernels to platform). Elapsed time: 00h 18m 15s 

[14:14:14] Starting logic optimization..
[14:14:14] Phase 1 Retarget
[14:14:14] Phase 2 Constant propagation
[14:14:14] Phase 3 Sweep
[14:14:44] Phase 4 BUFG optimization
[14:14:44] Phase 5 Shift Register Optimization
[14:14:44] Phase 6 Post Processing Netlist
[14:14:44] Finished 3rd of 6 tasks (FPGA logic optimization). Elapsed time: 00h 00m 30s 

[14:14:44] Starting logic placement..
[14:14:44] Phase 1 Placer Initialization
[14:14:44] Phase 1.1 Placer Initialization Netlist Sorting
[14:14:44] Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
[14:15:14] Phase 1.3 Build Placer Netlist Model
[14:15:45] Phase 1.4 Constrain Clocks/Macros
[14:15:45] Phase 2 Global Placement
[14:15:45] Phase 2.1 Floorplanning
[14:15:45] Phase 2.1.1 Partition Driven Placement
[14:15:45] Phase 2.1.1.1 PBP: Partition Driven Placement
[14:16:45] Phase 2.1.1.2 PBP: Clock Region Placement
[14:16:45] Phase 2.1.1.3 PBP: Compute Congestion
[14:16:45] Phase 2.1.1.4 PBP: UpdateTiming
[14:16:45] Phase 2.1.1.5 PBP: Add part constraints
[14:16:45] Phase 2.2 Update Timing before SLR Path Opt
[14:16:45] Phase 2.3 Post-Processing in Floorplanning
[14:16:45] Phase 2.4 Global Placement Core
[14:18:16] Phase 2.4.1 UpdateTiming Before Physical Synthesis
[14:18:16] Phase 2.4.2 Physical Synthesis In Placer
[14:18:46] Phase 3 Detail Placement
[14:18:46] Phase 3.1 Commit Multi Column Macros
[14:18:46] Phase 3.2 Commit Most Macros & LUTRAMs
[14:19:17] Phase 3.3 Small Shape DP
[14:19:17] Phase 3.3.1 Small Shape Clustering
[14:19:17] Phase 3.3.2 Flow Legalize Slice Clusters
[14:19:17] Phase 3.3.3 Slice Area Swap
[14:19:17] Phase 3.3.3.1 Slice Area Swap Initial
[14:19:47] Phase 3.4 Re-assign LUT pins
[14:19:47] Phase 3.5 Pipeline Register Optimization
[14:19:47] Phase 4 Post Placement Optimization and Clean-Up
[14:19:47] Phase 4.1 Post Commit Optimization
[14:20:17] Phase 4.1.1 Post Placement Optimization
[14:20:17] Phase 4.1.1.1 BUFG Insertion
[14:20:17] Phase 1 Physical Synthesis Initialization
[14:20:17] Phase 4.1.1.2 Post Placement Timing Optimization
[14:20:47] Phase 4.2 Post Placement Cleanup
[14:20:47] Phase 4.3 Placer Reporting
[14:20:47] Phase 4.3.1 Print Estimated Congestion
[14:20:47] Phase 4.4 Final Placement Cleanup
[14:21:18] Finished 4th of 6 tasks (FPGA logic placement). Elapsed time: 00h 06m 33s 

[14:21:18] Starting logic routing..
[14:21:48] Phase 1 Build RT Design
[14:22:18] Phase 2 Router Initialization
[14:22:18] Phase 2.1 Fix Topology Constraints
[14:22:18] Phase 2.2 Pre Route Cleanup
[14:22:18] Phase 2.3 Global Clock Net Routing
[14:22:18] Phase 2.4 Update Timing
[14:22:49] Phase 3 Initial Routing
[14:22:49] Phase 3.1 Global Routing
[14:23:19] Phase 4 Rip-up And Reroute
[14:23:19] Phase 4.1 Global Iteration 0
[14:33:24] Phase 4.2 Global Iteration 1
[14:33:24] Phase 5 Delay and Skew Optimization
[14:33:24] Phase 5.1 Delay CleanUp
[14:33:24] Phase 5.1.1 Update Timing
[14:33:54] Phase 5.1.2 Update Timing
[14:33:54] Phase 5.2 Clock Skew Optimization
[14:33:54] Phase 6 Post Hold Fix
[14:33:54] Phase 6.1 Hold Fix Iter
[14:33:54] Phase 6.1.1 Update Timing
[14:34:24] Phase 7 Route finalize
[14:34:24] Phase 8 Verifying routed nets
[14:34:24] Phase 9 Depositing Routes
[14:34:24] Phase 10 Resolve XTalk
[14:34:24] Phase 11 Route finalize
[14:34:24] Phase 12 Post Router Timing
[14:34:55] Finished 5th of 6 tasks (FPGA routing). Elapsed time: 00h 13m 37s 

[14:34:55] Starting bitstream generation..
[14:36:25] Creating bitmap...
Check VPL, containing 1 checks, has run: 0 errors
[14:36:43] Run vpl: Step impl: Completed
[14:36:43] Writing bitstream ./vitis_design_wrapper.bit...
[14:36:43] Finished 6th of 6 tasks (FPGA bitstream generation). Elapsed time: 00h 01m 48s 
[14:36:44] Run vpl: FINISHED. Run Status: impl Complete!
INFO: [v++ 60-1441] [14:36:44] Run run_link: Step vpl: Completed
Time (s): cpu = 00:00:19 ; elapsed = 00:40:47 . Memory (MB): peak = 446.852 ; gain = 0.000 ; free physical = 9086 ; free virtual = 15469
INFO: [v++ 60-1443] [14:36:44] Run run_link: Step rtdgen: Started
INFO: [v++ 60-1453] Command Line: rtdgen
INFO: [v++ 60-1454] Run Directory: /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/run_link
INFO: [v++ 60-1453] Command Line: cf2sw -a /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/int/address_map.xml -sdsl /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/int/sdsl.dat -xclbin /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/int/xclbin_orig.xml -rtd /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/int/binary_container_1.rtd -o /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/int/binary_container_1.xml
INFO: [v++ 60-1652] Cf2sw returned exit code: 0
INFO: [v++ 60-1441] [14:36:48] Run run_link: Step rtdgen: Completed
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 446.852 ; gain = 0.000 ; free physical = 9864 ; free virtual = 16253
INFO: [v++ 60-1443] [14:36:48] Run run_link: Step xclbinutil: Started
INFO: [v++ 60-1453] Command Line: xclbinutil --add-section BITSTREAM:RAW:/media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/int/system.bit --force --target hw --key-value SYS:dfx_enable:false --add-section :JSON:/media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/int/binary_container_1.rtd --add-section CLOCK_FREQ_TOPOLOGY:JSON:/media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/int/binary_container_1_xml.rtd --add-section BUILD_METADATA:JSON:/media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/int/binary_container_1_build.rtd --add-section EMBEDDED_METADATA:RAW:/media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/int/binary_container_1.xml --add-section SYSTEM_METADATA:RAW:/media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/int/systemDiagramModelSlrBaseAddress.json --key-value SYS:PlatformVBNV:xilinx.com_xd_xilinx_zcu102_base_202220_1_202220_1 --output /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/binary_container_1.xclbin
INFO: [v++ 60-1454] Run Directory: /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/run_link
XRT Build Version: 2.8.0 (2020.2)
       Build Date: 2022-10-30 14:58:06
          Hash ID: b94857f15ba8c8251df446e8c51af7e0a7c9e061
Creating a default 'in-memory' xclbin image.

Section: 'BITSTREAM'(0) was successfully added.
Size   : 26510905 bytes
Format : RAW
File   : '/media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/int/system.bit'

Section: 'MEM_TOPOLOGY'(6) was successfully added.
Format : JSON
File   : 'mem_topology'

Section: 'IP_LAYOUT'(8) was successfully added.
Format : JSON
File   : 'ip_layout'

Section: 'CONNECTIVITY'(7) was successfully added.
Format : JSON
File   : 'connectivity'
WARNING: Skipping CLOCK_FREQ_TOPOLOGY section for count size is zero.
WARNING: Section 'CLOCK_FREQ_TOPOLOGY' content is empty.  No data in the given JSON file.

Section: 'CLOCK_FREQ_TOPOLOGY'(11) was empty.  No action taken.
Format : JSON
File   : '/media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/int/binary_container_1_xml.rtd'

Section: 'BUILD_METADATA'(14) was successfully added.
Size   : 4904 bytes
Format : JSON
File   : '/media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/int/binary_container_1_build.rtd'

Section: 'EMBEDDED_METADATA'(2) was successfully added.
Size   : 5287 bytes
Format : RAW
File   : '/media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/int/binary_container_1.xml'

Section: 'SYSTEM_METADATA'(22) was successfully added.
Size   : 31196 bytes
Format : RAW
File   : '/media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/int/systemDiagramModelSlrBaseAddress.json'
Successfully wrote (26566894 bytes) to the output file: /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/binary_container_1.xclbin
Leaving xclbinutil.
INFO: [v++ 60-1441] [14:36:48] Run run_link: Step xclbinutil: Completed
Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.32 . Memory (MB): peak = 446.852 ; gain = 0.000 ; free physical = 9837 ; free virtual = 16253
INFO: [v++ 60-1443] [14:36:48] Run run_link: Step xclbinutilinfo: Started
INFO: [v++ 60-1453] Command Line: xclbinutil --quiet --force --info /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/binary_container_1.xclbin.info --input /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/binary_container_1.xclbin
INFO: [v++ 60-1454] Run Directory: /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/run_link
INFO: [v++ 60-1441] [14:36:48] Run run_link: Step xclbinutilinfo: Completed
Time (s): cpu = 00:00:00.31 ; elapsed = 00:00:00.34 . Memory (MB): peak = 446.852 ; gain = 0.000 ; free physical = 9836 ; free virtual = 16253
INFO: [v++ 60-1443] [14:36:48] Run run_link: Step generate_sc_driver: Started
INFO: [v++ 60-1453] Command Line: 
INFO: [v++ 60-1454] Run Directory: /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/link/run_link
INFO: [v++ 60-1441] [14:36:48] Run run_link: Step generate_sc_driver: Completed
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 446.852 ; gain = 0.000 ; free physical = 9836 ; free virtual = 16253
Check POST-VPL, containing 1 checks, has run: 0 errors
INFO: [v++ 60-244] Generating system estimate report...
INFO: [v++ 60-1092] Generated system estimate report: /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/reports/link/system_estimate_binary_container_1.xtxt
INFO: [v++ 60-2397] Platform default or user specified output type sd_card detected but is not a supported output for v++ --link. Use the v++ --package option instead to create SD card output.
INFO: [v++ 60-586] Created binary_container_1/binary_container_1.xclbin
INFO: [v++ 60-1307] Run completed. Additional information can be found in:
	Guidance: /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/reports/link/v++_link_binary_container_1_guidance.html
	Timing Report: /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/reports/link/imp/impl_1_vitis_design_wrapper_timing_summary_routed.rpt
	Vivado Log: /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/logs/link/vivado.log
	Steps Log File: /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/logs/link/link.steps.log

INFO: [v++ 60-2343] Use the vitis_analyzer tool to visualize and navigate the relevant reports. Run the following command. 
    vitis_analyzer /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/binary_container_1.xclbin.link_summary 
INFO: [v++ 60-791] Total elapsed time: 0h 41m 19s
INFO: [v++ 60-1653] Closing dispatch client.
v++ -t hw --platform /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/xilinx_zcu102_base_202220_1/xilinx_zcu102_base_202220_1.xpfm -p binary_container_1/binary_container_1.xclbin -o binary_container_1/dpu.xclbin --package.out_dir binary_container_1 --package.rootfs /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/xilinx-zynqmp-common-v2022.2_10141622/xilinx-zynqmp-common-v2022.2//rootfs.ext4 --package.sd_file /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/xilinx-zynqmp-common-v2022.2_10141622/xilinx-zynqmp-common-v2022.2//Image 
Option Map File Used: '/media/userpc/Storage_Dataset/opt5_2022/Vitis/2022.2/data/vitis/vpp/optMap.xml'

****** v++ v2022.2 (64-bit)
  **** SW Build 3671529 on 2022-10-13-17:52:11
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.

INFO: [v++ 60-1306] Additional information associated with this v++ package can be found at:
	Reports: /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/_x/reports/package
	Log files: /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/_x/logs/package
Running Dispatch Server on port: 33871
INFO: [v++ 60-1548] Creating build summary session with primary output /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/dpu.xclbin.package_summary, at Fri Mar 24 14:37:01 2023
INFO: [v++ 60-1315] Creating rulecheck session with output '/media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/_x/reports/package/v++_package_dpu_guidance.html', at Fri Mar 24 14:37:01 2023
INFO: [v++ 60-895]   Target platform: /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/xilinx_zcu102_base_202220_1/xilinx_zcu102_base_202220_1.xpfm
INFO: [v++ 60-1578]   This platform contains Xilinx Shell Archive '/media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/xilinx_zcu102_base_202220_1/hw/hw.xsa'
INFO: [v++ 60-2256] Packaging for hardware

Section: 'SYSTEM_METADATA'(22) was successfully written.
Format: RAW
File  : '/media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/_x/package/extractedSystemDiagram.json'

Section: 'BITSTREAM'(0) was successfully written.
Format: RAW
File  : '/media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/_x/package/system.bit'
INFO: [v++ 82-3881] device architecture set to zynqmp
WARNING: [v++ 82-1147] Kernel image is not specified for linux domain
INFO: [v++ 82-3883] generating bootimage for arch zynqmp with bif /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/xilinx_zcu102_base_202220_1.bif


****** Xilinx Bootgen v2022.2.0
  **** Build date : Oct 13 2022-12:22:43
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.

[WARNING]: [fsbl_config] a53_x64 | a53_x32 | r5_single | r5_dual is no more supported. Use 'destination_cpu' attribute for bootloader partition

[INFO]   : Bootimage generated successfully

INFO: [v++ 82-1011] creating sd_card directory
INFO: [v++ 82-3528] mkfsimage command run: /media/userpc/Storage_Dataset/opt5_2022/Vitis/2022.2/scripts/vitis/util/mkfsImage.sh -s /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/sd_card/ -o /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/sd_card.img -m 1 -e /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/xilinx-zynqmp-common-v2022.2_10141622/xilinx-zynqmp-common-v2022.2/rootfs.ext4
SDCARD_SIZE_KB: 74636
FAT_SDCARD_SIZE: 1048576
FATSIZE:1024
fat_start:63
fat_end:2096639
fat_sector:2096577
ext4_start:0
ext4_sector:5998550
EXT4SIZE:3072
TOTALSIZE:4096
dummy_ext4_sector:292906
sd_card_fat_start:2048
sd_card_ext4_start:2000896
dummy_ext4_start:7999446
2096577+0 records in
2096577+0 records out
1073447424 bytes (1.1 GB, 1.0 GiB) copied, 4.06444 s, 264 MB/s
5998550+0 records in
5998550+0 records out
3071257600 bytes (3.1 GB, 2.9 GiB) copied, 99.7087 s, 30.8 MB/s
292906+0 records in
292906+0 records out
149967872 bytes (150 MB, 143 MiB) copied, 0.536514 s, 280 MB/s

Section: 'SYSTEM_METADATA'(22) was successfully added.
Size   : 31232 bytes
Format : RAW
File   : '/media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/_x/package/packagedSystemDiagram.json'
Successfully wrote (26566926 bytes) to the output file: /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/_x/package/./.Xil/v++-23455-userPC-3476/upsert.xclbin
INFO: [v++ 60-2460] Successfully copied a temporary xclbin to the output xclbin: /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/dpu.xclbin
INFO: [v++ 60-2343] Use the vitis_analyzer tool to visualize and navigate the relevant reports. Run the following command. 
    vitis_analyzer /media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis/binary_container_1/dpu.xclbin.package_summary 
INFO: [v++ 60-791] Total elapsed time: 0h 2m 1s
INFO: [v++ 60-1653] Closing dispatch client.
cp ./binary_*/link/vivado/vpl/prj/prj*/sources_1/bd/*/hw_handoff/*.hwh ./binary_*/sd_card
cp ./binary_*/link/vivado/vpl/prj/prj.gen/sources_1/bd/*/ip/*_DPUCZDX8G_1_0/arch.json ./binary_*/sd_card
(base) userpc@userPC-3476:/media/userpc/Storage_Dataset/Kria_and_Vitis_AI_Forums/DPUCZDX8G_VAI_v3.0/prj/Vitis$

(base) logictronix@logictronix:~/Vitis_AI_latest/Vitis-AI$ ./docker_run.sh xilinx/vitis-ai-gpu:2.5
NOTICE:  BY INVOKING THIS SCRIPT AND USING THE SOFTWARE INSTALLED BY THE
SCRIPT, YOU AGREE ON BEHALF OF YOURSELF AND YOUR EMPLOYER (IF APPLICABLE)
TO BE BOUND TO THE LICENSE AGREEMENTS APPLICABLE TO THE SOFTWARE THAT YOU
INSTALL BY RUNNING THE SCRIPT.

Press any key to continue...
BY ELECTING TO CONTINUE, YOU WILL CAUSE THIS SCRIPT FILE TO AUTOMATICALLY
INSTALL A VARIETY OF SOFTWARE COPYRIGHTED
BY XILINX AND THIRD PARTIES THAT IS SUBJECT TO VARIOUS LICENSE AGREEMENTS 
THAT APPEAR UPON INSTALLATION, ACCEPTANCE AND/OR ACTIVATION OF THE
SOFTWARE AND/OR ARE CONTAINED OR DESCRIBED IN THE CORRESPONDING RELEASE
NOTES OR OTHER DOCUMENTATION OR HEADER OR SOURCE FILES. XILINX DOES NOT
GRANT TO LICENSEE ANY RIGHTS OR LICENSES TO SUCH THIRD-PARTY SOFTWARE.
LICENSEE AGREES TO CAREFULLY REVIEW AND ABIDE BY THE TERMS AND CONDITIONS
OF SUCH LICENSE AGREEMENTS TO THE EXTENT THAT THEY GOVERN SUCH SOFTWARE.

Press any key to continue...
BY ELECTING TO CONTINUE, YOU WILL CAUSE THE FOLLOWING SOFTWARE TO BE DOWNLOADED
AND INSTALLED ON YOUR SYSTEM. BY ELECTING TO CONTINUE, YOU UNDERSTAND THAT THE
INSTALLATION OF THE SOFTWARE LISTED BELOW MAY ALSO RESULT IN THE INSTALLATION
ON YOUR SYSTEM OF ADDITIONAL SOFTWARE NOT LISTED BELOW IN ORDER TO OPERATE
(SUCH SOFTWARE IS HEREAFTER REFERRED TO AS DEPENDENCIES)
XILINX DOES NOT GRANT TO LICENSEE ANY RIGHTS OR LICENSES TO SUCH DEPENDENCIES
LICENSEE AGREES TO CAREFULLY REVIEW AND ABIDE BY THE TERMS AND CONDITIONS
OF ANY LICENSE AGREEMENTS TO THE EXTENT THAT THEY GOVERN SUCH DEPENDENCIES

BY ELECTING TO CONTINUE, YOU WILL CAUSE THE FOLLOWING SOFTWARE PACKAGES
(AND THEIR RESPECTIVE DEPENDENCIES, IF APPLICABLE) TO BE DOWNLOADED FROM
UBUNTU'S MAIN REPO AND INSTALLED ON YOUR SYSTEM:
http://us.archive.ubuntu.com/ubuntu/dists/bionic/
Press any key to continue...http://us.archive.ubuntu.com/ubuntu/dists/bionic/
1.  sudo  
2.  git  
3.  zstd  
4.  tree  
5.  vim  
6.  wget  
7.  bzip2  
8.  ca-certificates  
9.  curl  
10. unzip  
11. python3-minimal  
12. python3-opencv  
13. python3-venv  
14. python3-pip  
15. python3-setuptools  
16. g++  
17. make  
18. cmake  
19. build-essential  
20. autoconf  
21. libgoogle-glog-dev  
22. libgflags-dev  
23. libunwind-dev  
24. libtool  
25. libgtk2.0-dev
26. libavcodec-dev
27. libavformat-dev
28. libavdevice-dev

BY ELECTING TO CONTINUE, YOU WILL CAUSE THE FOLLOWING SOFTWARE PACKAGES
(AND THEIR RESPECTIVE DEPENDENCIES, IF APPLICABLE) TO BE DOWNLOADED FROM
ANACONDA REPO AND INSTALLED ON YOUR SYSTEM:
https://anaconda.org
Press any key to continue...1.  absl-py
2.  astor
3.  attrs
4.  backcall
5.  backports
6.  backports.weakref
7.  blas
8.  bleach
9.  boost
10.  bzip2
11.  ca-certificates
12.  cairo
13.  c-ares
14.  certifi
15.  cffi
16.  chardet
17.  cloudpickle
18.  conda
19.  conda-package-handling
20.  cryptography
21.  cycler
22.  cytoolz
23.  dask-core
24.  dbus
25.  decorator
26.  defusedxml
27.  dill
28.  dpuv1_compiler
29.  dpuv1-rt
30.  dpuv1-rt-ext
31.  dpuv1-rt-neptune
32.  entrypoints
33.  expat
34.  ffmpeg
35.  fontconfig
36.  freeglut
37.  freetype
38.  fribidi
39.  gast
40.  gettext
41.  gflags
42.  giflib
43.  glib
44.  glog
45.  gmp
46.  gnutls
47.  google-pasta
48.  graphite2
49.  graphviz
50.  grpcio
51.  gst-plugins-base
52.  gstreamer
53.  h5py
54.  harfbuzz
55.  hdf5
56.  icu
57.  idna
58.  imageio
59.  importlib_metadata
60.  importlib-metadata
61.  intel-openmp
62.  ipykernel
63.  ipython
64.  ipython_genutils
65.  ipywidgets
66.  jasper
67.  jedi
68.  jinja2
69.  joblib
70.  jpeg
71.  json-c
72.  jsoncpp
73.  jsonschema
74.  jupyter
75.  jupyter_client
76.  jupyter_console
77.  jupyter_core
78.  keras
79.  keras-applications
80.  keras-base
81.  keras-preprocessing
82.  kiwisolver
83.  krb5
84.  lame
85.  ld_impl_linux-64
86.  leveldb
87.  libblas
88.  libboost
89.  libcblas
90.  libedit
91.  libffi
92.  _libgcc_mutex
93.  libgcc-ng
94.  libgfortran-ng
95.  libglu
96.  libiconv
97.  liblapack
98.  liblapacke
99.  libopenblas
100.  libopencv
101.  libopus
102.  libpng
103.  libprotobuf
104.  libsodium
105.  libssh2
106.  libstdcxx-ng
107.  libtiff
108.  libtool
109.  libuuid
110.  libvpx
111.  libwebp
112.  libxcb
113.  libxml2
114.  lmdb
115.  lz4-c
116.  markdown
117.  markupsafe
118.  marshmallow
119.  matplotlib
120.  matplotlib-base
121.  mistune
122.  mkl
123.  mkl_fft
124.  mkl_random
125.  mkl-service
126.  mock
127.  more-itertools
128.  nbconvert
129.  nbformat
130.  ncurses
131.  nettle
132.  networkx
133.  notebook
134.  numpy
135.  numpy-base
136.  olefile
137.  openblas
138.  opencv
139.  openh264
140.  openssl
141.  opt_einsum
142.  packaging
143.  pandas
144.  pandoc
145.  pandocfilters
146.  pango
147.  parso
148.  pexpect
149.  pickleshare
150.  pillow
151.  pip
152.  pixman
153.  pluggy
154.  progressbar2
155.  prometheus_client
156.  prompt_toolkit
157.  prompt-toolkit
158.  protobuf
159.  ptyprocess
160.  py
161.  pybind11
162.  py-boost
163.  pycosat
Press any key to continue...163.  pycosat
164.  pycparser
165.  pydot
166.  pygments
167.  py-opencv
168.  pyopenssl
169.  pyparsing
170.  pyqt
171.  pyrsistent
172.  pysocks
173.  pytest
174.  pytest-runner
175.  python
176.  python-dateutil
177.  python-gflags
178.  python-graphviz
179.  python-leveldb
180.  python-utils
181.  pytz
182.  pywavelets
183.  pyyaml
184.  pyzmq
185.  qt
186.  qtconsole
187.  qtpy
188.  readline
189.  requests
190.  ruamel_yaml
191.  scikit-image
192.  scikit-learn
193.  scipy
194.  send2trash
195.  setuptools
196.  sip
197.  six
198.  snappy
199.  sqlite
200.  tensorboard
201.  tensorflow
202.  tensorflow-base
203.  tensorflow-estimator
204.  termcolor
205.  terminado
206.  testpath
207.  _tflow_select
208.  threadpoolctl
209.  tk
210.  toolz
211.  tornado
212.  tqdm
213.  traitlets
214.  urllib3
215.  wcwidth
216.  webencodings
217.  werkzeug
218.  wheel
219.  widgetsnbextension
220.  wrapt
221.  x264
222.  xcompiler
223.  xorg-libice
224.  xorg-libsm
225.  xorg-libx11
226.  xorg-libxext
227.  xorg-libxpm
228.  xorg-libxrender
229.  xorg-libxt
230.  xorg-renderproto
231.  xorg-xextproto
232.  xorg-xproto
233.  xz
234.  yaml
235.  yaml-cpp
236.  zeromq
237.  zipp
238.  zlib
239.  zstd

BY ELECTING TO CONTINUE, YOU ACKNOWLEDGE AND AGREE, FOR YOURSELF AND ON BEHALF
OF YOUR EMPLOYER (IF APPLICABLE), THAT XILINX IS NOT DISTRIBUTING TO YOU IN
THIS FILE ANY OF THE AFORMENTIONED SOFTWARE OR DEPENDENCIES, AND THAT YOU ARE
SOLELY RESPONSIBLE FOR THE INSTALLATION OF SUCH SOFTWARE AND DEPENDENCIES ON
YOUR SYSTEM AND FOR CAREFULLY REVIEWING AND ABIDING BY THE TERMS AND CONDITIONS
OF ANY LICENSE AGREEMENTS TO THE EXTENT THAT THEY GOVERN SUCH SOFTWARE AND DEPENDENCIES

Press any key to continue...

Do you agree to the terms and wish to proceed [y/n]? y
Setting up logictronix 's environment in the Docker container...
usermod: no changes
Running as vitis-ai-user with ID 0 and group 0 


==========================================
 
__      ___ _   _                   _____
\ \    / (_) | (_)            /\   |_   _|
 \ \  / / _| |_ _ ___ ______ /  \    | |
  \ \/ / | | __| / __|______/ /\ \   | |
   \  /  | | |_| \__ \     / ____ \ _| |_
    \/   |_|\__|_|___/    /_/    \_\_____|
 
==========================================

Docker Image Version: 2.5.0.1260   (GPU) 
Vitis AI Git Hash: 491faef6e 
Build Date: 2023-02-10

For TensorFlow 1.15 Workflows do:
     conda activate vitis-ai-tensorflow 
For PyTorch Workflows do:
     conda activate vitis-ai-pytorch 
For TensorFlow 2.8 Workflows do:
     conda activate vitis-ai-tensorflow2 
For Darknet Optimizer Workflows do:
     conda activate vitis-ai-optimizer_darknet 
For PyTorch Optimizer Workflows do:
     conda activate vitis-ai-optimizer_pytorch 
For TensorFlow 1.15 Optimizer Workflows do:
     conda activate vitis-ai-optimizer_tensorflow 
For TensorFlow 2.8 Optimizer Workflows do:
     conda activate vitis-ai-optimizer_tensorflow2 
Vitis-AI /workspace > conda activate vitis-ai-tensorflow
(vitis-ai-tensorflow) Vitis-AI /workspace > cd quantize_compile/tf_resnetv1_50_imagenet_224_224_6.97G_3.0/
(vitis-ai-tensorflow) Vitis-AI /workspace/quantize_compile/tf_resnetv1_50_imagenet_224_224_6.97G_3.0 > 
(vitis-ai-tensorflow) Vitis-AI /workspace/quantize_compile/tf_resnetv1_50_imagenet_224_224_6.97G_3.0 > vai_c_tensorflow --arch ./arch_zcu102_2xb512_march2023.json  -f quantized/quantized_baseline_6.96B_919.pb --output_dir compile_result_zcu102 -n tf_resnet50
**************************************************
* VITIS_AI Compilation - Xilinx Inc.
**************************************************
[INFO] Namespace(batchsize=1, inputs_shape=None, layout='NHWC', model_files=['quantized/quantized_baseline_6.96B_919.pb'], model_type='tensorflow', named_inputs_shape=None, out_filename='/tmp/tf_resnet50_0x101000056010200_org.xmodel', proto=None)
[INFO] tensorflow model: /workspace/quantize_compile/tf_resnetv1_50_imagenet_224_224_6.97G_3.0/quantized/quantized_baseline_6.96B_919.pb
[INFO] parse raw model     :100%|| 270/270 [00:00<00:00, 11919.65it/s]             
[INFO] infer shape (NHWC)  :100%|| 331/331 [00:00<00:00, 3840.81it/s]              
[INFO] perform level-0 opt :100%|| 3/3 [00:00<00:00, 196.80it/s]                   
[INFO] perform level-1 opt :100%|| 7/7 [00:00<00:00, 226.36it/s]                   
[INFO] generate xmodel     :100%|| 219/219 [00:00<00:00, 1251.45it/s]              
[INFO] dump xmodel: /tmp/tf_resnet50_0x101000056010200_org.xmodel
[UNILOG][INFO] Compile mode: dpu
[UNILOG][INFO] Debug mode: function
[UNILOG][INFO] Target architecture: DPUCZDX8G_ISA1_B512_0101000056010200
[UNILOG][INFO] Graph name: quantized_baseline_6.96B_919, with op num: 435
[UNILOG][INFO] Begin to compile...
[UNILOG][INFO] Total device subgraph number 3, DPU subgraph number 1
[UNILOG][INFO] Compile done.
[UNILOG][INFO] The meta json is saved to "/workspace/quantize_compile/tf_resnetv1_50_imagenet_224_224_6.97G_3.0/compile_result_zcu102/meta.json"
[UNILOG][INFO] The compiled xmodel is saved to "/workspace/quantize_compile/tf_resnetv1_50_imagenet_224_224_6.97G_3.0/compile_result_zcu102/tf_resnet50.xmodel"
[UNILOG][INFO] The compiled xmodel's md5sum is c3131f7d1cdbae1daedb7661d8323dad, and has been saved to "/workspace/quantize_compile/tf_resnetv1_50_imagenet_224_224_6.97G_3.0/compile_result_zcu102/md5sum.txt"
(vitis-ai-tensorflow) Vitis-AI /workspace/quantize_compile/tf_resnetv1_50_imagenet_224_224_6.97G_3.0 >

Xilinx Zynq MP First Stage Boot Loader
Release 2022.2   Oct 11 2022  -  22:39:26
NOTICE:  BL31: v2.6(release):xlnx_rebase_v2.6_2022.1_update3-18-g0897efd45
NOTICE:  BL31: Built : 03:55:03, Sep  9 2022


U-Boot 2022.01 (Sep 20 2022 - 06:35:33 +0000)

CPU:   ZynqMP
Silicon: v3
Model: ZynqMP ZCU102 Rev1.0
Board: Xilinx ZynqMP
DRAM:  4 GiB
PMUFW:  v1.1
PMUFW no permission to change config object
EL Level:       EL2
Chip ID:        zu9eg
NAND:  0 MiB
MMC:   mmc@ff170000: 0
Loading Environment from FAT... *** Error - No Valid Environment Area found
*** Warning - bad env area, using default environment

In:    serial
Out:   serial
Err:   serial
Bootmode: LVL_SHFT_SD_MODE1
Reset reason:   EXTERNAL
Net:   FEC: can't find phy-handle

ZYNQ GEM: ff0e0000, mdio bus ff0e0000, phyaddr 12, interface rgmii-id
eth0: ethernet@ff0e0000
scanning bus for devices...
SATA link 0 timeout.
SATA link 1 timeout.
AHCI 0001.0301 32 slots 2 ports 6 Gbps 0x3 impl SATA mode
flags: 64bit ncq pm clo only pmp fbss pio slum part ccc apst
starting USB...
Bus usb@fe200000: Register 2000440 NbrPorts 2
Starting the controller
USB XHCI 1.00
scanning bus usb@fe200000 for devices... 1 USB Device(s) found
       scanning usb for storage devices... 0 Storage Device(s) found
Hit any key to stop autoboot:  0
switch to partitions #0, OK
mmc0 is current device
Scanning mmc 0:1...
Found U-Boot script /boot.scr
2777 bytes read in 17 ms (159.2 KiB/s)
## Executing script at 20000000
Trying to load boot images from mmc0
21592576 bytes read in 1598 ms (12.9 MiB/s)
## Flattened Device Tree blob at 00100000
   Booting using the fdt blob at 0x100000
   Loading Device Tree to 000000007bbed000, end 000000007bbfa1a6 ... OK

Starting kernel ...

[    0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
[    0.000000] Linux version 5.15.36-xilinx-v2022.2 (oe-user@oe-host) (aarch64-xilinx-linux-gcc (GCC) 11.2.0, GNU ld (GNU Binutils) 2.37.20210721) #1 SMP Mon Oct 3 07:50:07 UTC 2022
[    0.000000] Machine model: ZynqMP ZCU102 Rev1.0
[    0.000000] earlycon: cdns0 at MMIO 0x00000000ff000000 (options '115200n8')
[    0.000000] printk: bootconsole [cdns0] enabled
[    0.000000] efi: UEFI not found.
[    0.000000] Zone ranges:
[    0.000000]   DMA32    [mem 0x0000000000000000-0x00000000ffffffff]
[    0.000000]   Normal   [mem 0x0000000100000000-0x000000087fffffff]
[    0.000000] Movable zone start for each node
[    0.000000] Early memory node ranges
[    0.000000]   node   0: [mem 0x0000000000000000-0x000000007fefffff]
[    0.000000]   node   0: [mem 0x0000000800000000-0x000000087fffffff]
[    0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x000000087fffffff]
[    0.000000] On node 0, zone Normal: 256 pages in unavailable ranges
[    0.000000] cma: Reserved 1536 MiB at 0x0000000017800000
[    0.000000] psci: probing for conduit method from DT.
[    0.000000] psci: PSCIv1.1 detected in firmware.
[    0.000000] psci: Using standard PSCI v0.2 function IDs
[    0.000000] psci: MIGRATE_INFO_TYPE not supported.
[    0.000000] psci: SMC Calling Convention v1.2
[    0.000000] percpu: Embedded 18 pages/cpu s34776 r8192 d30760 u73728
[    0.000000] Detected VIPT I-cache on CPU0
[    0.000000] CPU features: detected: ARM erratum 845719
[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 1031940
[    0.000000] Kernel command line: earlycon console=ttyPS0,115200 clk_ignore_unused root=/dev/mmcblk0p2 rw rootwait cma=1536M
[    0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
[    0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
[    0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
[    0.000000] software IO TLB: mapped [mem 0x0000000013800000-0x0000000017800000] (64MB)
[    0.000000] Memory: 358888K/4193280K available (13888K kernel code, 990K rwdata, 3916K rodata, 2176K init, 573K bss, 2261528K reserved, 1572864K cma-reserved)
[    0.000000] rcu: Hierarchical RCU implementation.
[    0.000000] rcu:     RCU event tracing is enabled.
[    0.000000] rcu:     RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=4.
[    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
[    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
[    0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
[    0.000000] GIC: Adjusting CPU interface base to 0x00000000f902f000
[    0.000000] Root IRQ handler: gic_handle_irq
[    0.000000] GIC: Using split EOI/Deactivate mode
[    0.000000] random: get_random_bytes called from start_kernel+0x474/0x6d8 with crng_init=0
[    0.000000] arch_timer: cp15 timer(s) running at 100.00MHz (phys).
[    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x171024e7e0, max_idle_ns: 440795205315 ns
[    0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 4398046511100ns
[    0.008442] Console: colour dummy device 80x25
[    0.012485] Calibrating delay loop (skipped), value calculated using timer frequency.. 200.00 BogoMIPS (lpj=400000)
[    0.022839] pid_max: default: 32768 minimum: 301
[    0.027646] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
[    0.034787] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
[    0.043641] rcu: Hierarchical SRCU implementation.
[    0.047628] EFI services will not be available.
[    0.051967] smp: Bringing up secondary CPUs ...
[    0.056703] Detected VIPT I-cache on CPU1
[    0.056744] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
[    0.057141] Detected VIPT I-cache on CPU2
[    0.057166] CPU2: Booted secondary processor 0x0000000002 [0x410fd034]
[    0.057547] Detected VIPT I-cache on CPU3
[    0.057570] CPU3: Booted secondary processor 0x0000000003 [0x410fd034]
[    0.057614] smp: Brought up 1 node, 4 CPUs
[    0.091778] SMP: Total of 4 processors activated.
[    0.096450] CPU features: detected: 32-bit EL0 Support
[    0.101554] CPU features: detected: CRC32 instructions
[    0.106694] CPU: All CPU(s) started at EL2
[    0.110737] alternatives: patching kernel code
[    0.116106] devtmpfs: initialized
[    0.124457] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
[    0.128554] futex hash table entries: 1024 (order: 4, 65536 bytes, linear)
[    0.173244] pinctrl core: initialized pinctrl subsystem
[    0.173754] DMI not present or invalid.
[    0.176914] NET: Registered PF_NETLINK/PF_ROUTE protocol family
[    0.183619] DMA: preallocated 256 KiB GFP_KERNEL pool for atomic allocations
[    0.189608] DMA: preallocated 256 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
[    0.197446] audit: initializing netlink subsys (disabled)
[    0.202848] audit: type=2000 audit(0.144:1): state=initialized audit_enabled=0 res=1
[    0.203230] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
[    0.217267] ASID allocator initialised with 65536 entries
[    0.222688] Serial: AMBA PL011 UART driver
[    0.249340] HugeTLB registered 1.00 GiB page size, pre-allocated 0 pages
[    0.250401] HugeTLB registered 32.0 MiB page size, pre-allocated 0 pages
[    0.257070] HugeTLB registered 2.00 MiB page size, pre-allocated 0 pages
[    0.263725] HugeTLB registered 64.0 KiB page size, pre-allocated 0 pages
[    1.339680] cryptd: max_cpu_qlen set to 1000
[    1.363777] DRBG: Continuing without Jitter RNG
[    1.467210] raid6: neonx8   gen()  2128 MB/s
[    1.535264] raid6: neonx8   xor()  1584 MB/s
[    1.603328] raid6: neonx4   gen()  2169 MB/s
[    1.671383] raid6: neonx4   xor()  1554 MB/s
[    1.739453] raid6: neonx2   gen()  2066 MB/s
[    1.807511] raid6: neonx2   xor()  1430 MB/s
[    1.875572] raid6: neonx1   gen()  1761 MB/s
[    1.943630] raid6: neonx1   xor()  1212 MB/s
[    2.011705] raid6: int64x8  gen()  1354 MB/s
[    2.079768] raid6: int64x8  xor()   773 MB/s
[    2.147843] raid6: int64x4  gen()  1597 MB/s
[    2.215889] raid6: int64x4  xor()   854 MB/s
[    2.283963] raid6: int64x2  gen()  1396 MB/s
[    2.352023] raid6: int64x2  xor()   750 MB/s
[    2.420104] raid6: int64x1  gen()  1031 MB/s
[    2.488141] raid6: int64x1  xor()   517 MB/s
[    2.488181] raid6: using algorithm neonx4 gen() 2169 MB/s
[    2.492132] raid6: .... xor() 1554 MB/s, rmw enabled
[    2.497067] raid6: using neon recovery algorithm
[    2.502207] iommu: Default domain type: Translated
[    2.506499] iommu: DMA domain TLB invalidation policy: strict mode
[    2.512942] SCSI subsystem initialized
[    2.516579] usbcore: registered new interface driver usbfs
[    2.521920] usbcore: registered new interface driver hub
[    2.527193] usbcore: registered new device driver usb
[    2.532254] mc: Linux media interface: v0.10
[    2.536441] videodev: Linux video capture interface: v2.00
[    2.541907] pps_core: LinuxPPS API ver. 1 registered
[    2.546805] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[    2.555896] PTP clock support registered
[    2.559799] EDAC MC: Ver: 3.0.0
[    2.563174] zynqmp-ipi-mbox mailbox@ff990400: Registered ZynqMP IPI mbox with TX/RX channels.
[    2.571579] FPGA manager framework
[    2.574869] Advanced Linux Sound Architecture Driver Initialized.
[    2.581116] Bluetooth: Core ver 2.22
[    2.584357] NET: Registered PF_BLUETOOTH protocol family
[    2.589624] Bluetooth: HCI device and connection manager initialized
[    2.595940] Bluetooth: HCI socket layer initialized
[    2.600783] Bluetooth: L2CAP socket layer initialized
[    2.605805] Bluetooth: SCO socket layer initialized
[    2.610983] clocksource: Switched to clocksource arch_sys_counter
[    2.616827] VFS: Disk quotas dquot_6.6.0
[    2.620624] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
[    2.631908] NET: Registered PF_INET protocol family
[    2.632385] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
[    2.641203] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
[    2.648141] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
[    2.656169] TCP bind hash table entries: 32768 (order: 7, 524288 bytes, linear)
[    2.663631] TCP: Hash tables configured (established 32768 bind 32768)
[    2.669791] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
[    2.676453] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
[    2.683611] NET: Registered PF_UNIX/PF_LOCAL protocol family
[    2.689408] RPC: Registered named UNIX socket transport module.
[    2.694987] RPC: Registered udp transport module.
[    2.699653] RPC: Registered tcp transport module.
[    2.704321] RPC: Registered tcp NFSv4.1 backchannel transport module.
[    2.710728] PCI: CLS 0 bytes, default 64
[    2.714945] armv8-pmu pmu: hw perfevents: no interrupt-affinity property, guessing.
[    2.722406] hw perfevents: enabled with armv8_pmuv3 PMU driver, 7 counters available
[    2.745767] Initialise system trusted keyrings
[    2.745894] workingset: timestamp_bits=46 max_order=19 bucket_order=0
[    2.751708] NFS: Registering the id_resolver key type
[    2.756013] Key type id_resolver registered
[    2.760150] Key type id_legacy registered
[    2.764143] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
[    2.770788] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
[    2.778157] jffs2: version 2.2. (NAND) (SUMMARY)   2001-2006 Red Hat, Inc.
[    2.822428] NET: Registered PF_ALG protocol family
[    2.822479] xor: measuring software checksum speed
[    2.830510]    8regs           :  2363 MB/sec
[    2.834175]    32regs          :  2799 MB/sec
[    2.839252]    arm64_neon      :  2308 MB/sec
[    2.839308] xor: using function: 32regs (2799 MB/sec)
[    2.844332] Key type asymmetric registered
[    2.848396] Asymmetric key parser 'x509' registered
[    2.853277] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 244)
[    2.860598] io scheduler mq-deadline registered
[    2.865090] io scheduler kyber registered
[    2.869379] irq-xilinx: mismatch in kind-of-intr param
[    2.874177] irq-xilinx: /amba_pl@0/interrupt-controller@80020000: num_irq=32, sw_irq=0, edge=0x1
[    2.910807] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[    2.912708] Serial: AMBA driver
[    2.915605] cacheinfo: Unable to detect cache hierarchy for CPU 0
[    2.924996] brd: module loaded
[    2.928533] loop: module loaded
[    2.929587] mtdoops: mtd device (mtddev=name/number) must be supplied
[    2.936165] tun: Universal TUN/TAP device driver, 1.6
[    2.938325] CAN device driver interface
[    2.942921] usbcore: registered new interface driver asix
[    2.947463] usbcore: registered new interface driver ax88179_178a
[    2.953496] usbcore: registered new interface driver cdc_ether
[    2.959292] usbcore: registered new interface driver net1080
[    2.964917] usbcore: registered new interface driver cdc_subset
[    2.970798] usbcore: registered new interface driver zaurus
[    2.976342] usbcore: registered new interface driver cdc_ncm
[    2.982753] usbcore: registered new interface driver uas
[    2.987242] usbcore: registered new interface driver usb-storage
[    2.993851] rtc_zynqmp ffa60000.rtc: registered as rtc0
[    2.998382] rtc_zynqmp ffa60000.rtc: setting system clock to 1970-02-19T15:23:09 UTC (4288989)
[    3.007002] i2c_dev: i2c /dev entries driver
[    3.013244] usbcore: registered new interface driver uvcvideo
[    3.017832] Bluetooth: HCI UART driver ver 2.3
[    3.021295] Bluetooth: HCI UART protocol H4 registered
[    3.026396] Bluetooth: HCI UART protocol BCSP registered
[    3.031686] Bluetooth: HCI UART protocol LL registered
[    3.036776] Bluetooth: HCI UART protocol ATH3K registered
[    3.042151] Bluetooth: HCI UART protocol Three-wire (H5) registered
[    3.048406] Bluetooth: HCI UART protocol Intel registered
[    3.053743] Bluetooth: HCI UART protocol QCA registered
[    3.058947] usbcore: registered new interface driver bcm203x
[    3.064566] usbcore: registered new interface driver bpa10x
[    3.070105] usbcore: registered new interface driver bfusb
[    3.075554] usbcore: registered new interface driver btusb
[    3.081015] usbcore: registered new interface driver ath3k
[    3.086507] EDAC MC: ECC not enabled
[    3.090114] EDAC DEVICE0: Giving out device to module edac controller cache_err: DEV edac (POLLED)
[    3.099062] EDAC DEVICE1: Giving out device to module zynqmp-ocm-edac controller zynqmp_ocm: DEV ff960000.memory-controller (INTERRUPT)
[    3.111485] sdhci: Secure Digital Host Controller Interface driver
[    3.117140] sdhci: Copyright(c) Pierre Ossman
[    3.121461] sdhci-pltfm: SDHCI platform and OF driver helper
[    3.127493] ledtrig-cpu: registered to indicate activity on CPUs
[    3.133156] SMCCC: SOC_ID: ARCH_SOC_ID not implemented, skipping ....
[    3.139524] zynqmp_firmware_probe Platform Management API v1.1
[    3.145253] zynqmp_firmware_probe Trustzone version v1.0
[    3.180800] securefw securefw: securefw probed
[    3.180948] zynqmp_aes firmware:zynqmp-firmware:zynqmp-aes: The zynqmp-aes driver shall be deprecated in 2022.2 and removed in 2023.1
[    3.191795] alg: No test for xilinx-zynqmp-aes (zynqmp-aes)
[    3.197200] zynqmp_aes firmware:zynqmp-firmware:zynqmp-aes: AES Successfully Registered
[    3.205260] zynqmp-keccak-384 firmware:zynqmp-firmware:sha384: The zynqmp-sha-deprecated driver shall be deprecated in 2022.2 and removed in 2023.1 release
[    3.219041] alg: No test for xilinx-keccak-384 (zynqmp-keccak-384)
[    3.225314] alg: No test for xilinx-zynqmp-rsa (zynqmp-rsa)
[    3.230797] usbcore: registered new interface driver usbhid
[    3.236188] usbhid: USB HID core driver
[    3.243219] ARM CCI_400_r1 PMU driver probed
[    3.243909] fpga_manager fpga0: Xilinx ZynqMP FPGA Manager registered
[    3.251093] usbcore: registered new interface driver snd-usb-audio
[    3.257688] pktgen: Packet Generator for packet performance testing. Version: 2.75
[    3.265048] Initializing XFRM netlink socket
[    3.268610] NET: Registered PF_INET6 protocol family
[    3.273926] Segment Routing with IPv6
[    3.277126] In-situ OAM (IOAM) with IPv6
[    3.281059] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
[    3.287213] NET: Registered PF_PACKET protocol family
[    3.291902] NET: Registered PF_KEY protocol family
[    3.296661] can: controller area network core
[    3.301001] NET: Registered PF_CAN protocol family
[    3.305732] can: raw protocol
[    3.308674] can: broadcast manager protocol
[    3.312827] can: netlink gateway - max_hops=1
[    3.317219] Bluetooth: RFCOMM TTY layer initialized
[    3.322001] Bluetooth: RFCOMM socket layer initialized
[    3.327108] Bluetooth: RFCOMM ver 1.11
[    3.330814] Bluetooth: BNEP (Ethernet Emulation) ver 1.3
[    3.336091] Bluetooth: BNEP filters: protocol multicast
[    3.341285] Bluetooth: BNEP socket layer initialized
[    3.346212] Bluetooth: HIDP (Human Interface Emulation) ver 1.2
[    3.352095] Bluetooth: HIDP socket layer initialized
[    3.357053] 8021q: 802.1Q VLAN Support v1.8
[    3.361302] 9pnet: Installing 9P2000 support
[    3.365433] Key type dns_resolver registered
[    3.369787] registered taskstats version 1
[    3.373723] Loading compiled-in X.509 certificates
[    3.379630] Btrfs loaded, crc32c=crc32c-generic, zoned=no, fsverity=no
[    3.394207] ff000000.serial: ttyPS0 at MMIO 0xff000000 (irq = 62, base_baud = 6249999) is a xuartps
[    3.403240] printk: console [ttyPS0] enabled
[    3.403240] printk: console [ttyPS0] enabled
[    3.407542] printk: bootconsole [cdns0] disabled
[    3.407542] printk: bootconsole [cdns0] disabled
[    3.417111] ff010000.serial: ttyPS1 at MMIO 0xff010000 (irq = 63, base_baud = 6249999) is a xuartps
[    3.430295] of-fpga-region fpga-full: FPGA Region probed
[    3.437984] xilinx-zynqmp-dma fd500000.dma-controller: ZynqMP DMA driver Probe success
[    3.446072] xilinx-zynqmp-dma fd510000.dma-controller: ZynqMP DMA driver Probe success
[    3.454154] xilinx-zynqmp-dma fd520000.dma-controller: ZynqMP DMA driver Probe success
[    3.462238] xilinx-zynqmp-dma fd530000.dma-controller: ZynqMP DMA driver Probe success
[    3.470324] xilinx-zynqmp-dma fd540000.dma-controller: ZynqMP DMA driver Probe success
[    3.478409] xilinx-zynqmp-dma fd550000.dma-controller: ZynqMP DMA driver Probe success
[    3.486503] xilinx-zynqmp-dma fd560000.dma-controller: ZynqMP DMA driver Probe success
[    3.494597] xilinx-zynqmp-dma fd570000.dma-controller: ZynqMP DMA driver Probe success
[    3.502752] xilinx-zynqmp-dma ffa80000.dma-controller: ZynqMP DMA driver Probe success
[    3.510836] xilinx-zynqmp-dma ffa90000.dma-controller: ZynqMP DMA driver Probe success
[    3.518916] xilinx-zynqmp-dma ffaa0000.dma-controller: ZynqMP DMA driver Probe success
[    3.527016] xilinx-zynqmp-dma ffab0000.dma-controller: ZynqMP DMA driver Probe success
[    3.535111] xilinx-zynqmp-dma ffac0000.dma-controller: ZynqMP DMA driver Probe success
[    3.543198] xilinx-zynqmp-dma ffad0000.dma-controller: ZynqMP DMA driver Probe success
[    3.551280] xilinx-zynqmp-dma ffae0000.dma-controller: ZynqMP DMA driver Probe success
[    3.559370] xilinx-zynqmp-dma ffaf0000.dma-controller: ZynqMP DMA driver Probe success
[    3.567686] xilinx-zynqmp-dpdma fd4c0000.dma-controller: Xilinx DPDMA engine is probed
[    3.576267] spi-nor spi0.0: found mt25qu512a, expected m25p80
[    3.582311] spi-nor spi0.0: mt25qu512a (131072 Kbytes)
[    3.587475] 3 fixed-partitions partitions found on MTD device spi0.0
[    3.593826] Creating 3 MTD partitions on "spi0.0":
[    3.598612] 0x000000000000-0x000001e00000 : "boot"
[    3.604234] 0x000001e00000-0x000001e40000 : "bootenv"
[    3.609987] 0x000001e40000-0x000004240000 : "kernel"
[    3.616518] xilinx_can ff070000.can can0: TDC Offset value not in range
[    3.624735] macb ff0e0000.ethernet: Not enabling partial store and forward
[    3.633042] macb ff0e0000.ethernet eth0: Cadence GEM rev 0x50070106 at 0xff0e0000 irq 39 (00:0a:35:00:22:01)
[    3.643190] xilinx-axipmon ffa00000.perf-monitor: Probed Xilinx APM
[    3.649717] xilinx-axipmon fd0b0000.perf-monitor: Probed Xilinx APM
[    3.656216] xilinx-axipmon fd490000.perf-monitor: Probed Xilinx APM
[    3.662709] xilinx-axipmon ffa10000.perf-monitor: Probed Xilinx APM
[    3.669998] pca953x 0-0020: supply vcc not found, using dummy regulator
[    3.676691] pca953x 0-0020: using no AI
[    3.681195] pca953x 0-0021: supply vcc not found, using dummy regulator
[    3.687879] pca953x 0-0021: using no AI
[    3.700804] i2c i2c-0: Added multiplexed i2c bus 2
[    3.712214] i2c i2c-0: Added multiplexed i2c bus 3
[    3.728652] random: fast init done
[    3.770377] i2c i2c-0: Added multiplexed i2c bus 4
[    3.775291] i2c i2c-0: Added multiplexed i2c bus 5
[    3.780085] pca954x 0-0075: registered 4 multiplexed busses for I2C mux pca9544
[    3.787448] cdns-i2c ff020000.i2c: 400 kHz mmio ff020000 irq 41
[    3.794822] at24 6-0054: supply vcc not found, using dummy regulator
[    3.801728] at24 6-0054: 1024 byte 24c08 EEPROM, writable, 1 bytes/write
[    3.808472] i2c i2c-1: Added multiplexed i2c bus 6
[    3.813810] si5341 7-0036: no regulator set, defaulting vdd_sel to 2.5V for out
[    3.821115] si5341 7-0036: no regulator set, defaulting vdd_sel to 2.5V for out
[    3.828420] si5341 7-0036: no regulator set, defaulting vdd_sel to 2.5V for out
[    3.835719] si5341 7-0036: no regulator set, defaulting vdd_sel to 2.5V for out
[    3.843019] si5341 7-0036: no regulator set, defaulting vdd_sel to 2.5V for out
[    3.850320] si5341 7-0036: no regulator set, defaulting vdd_sel to 2.5V for out
[    3.857624] si5341 7-0036: no regulator set, defaulting vdd_sel to 2.5V for out
[    3.864928] si5341 7-0036: no regulator set, defaulting vdd_sel to 2.5V for out
[    3.873329] si5341 7-0036: Chip: 5341 Grade: 1 Rev: 1
[    3.911540] i2c i2c-1: Added multiplexed i2c bus 7
[    3.919157] si570 8-005d: registered, current frequency 300000000 Hz
[    3.925545] i2c i2c-1: Added multiplexed i2c bus 8
[    3.945284] si570 9-005d: registered, current frequency 148500000 Hz
[    3.951671] i2c i2c-1: Added multiplexed i2c bus 9
[    3.956670] si5324 10-0069: si5328 probed
[    4.023306] si5324 10-0069: si5328 probe successful
[    4.028225] i2c i2c-1: Added multiplexed i2c bus 10
[    4.033220] i2c i2c-1: Added multiplexed i2c bus 11
[    4.038214] i2c i2c-1: Added multiplexed i2c bus 12
[    4.043211] i2c i2c-1: Added multiplexed i2c bus 13
[    4.048088] pca954x 1-0074: registered 8 multiplexed busses for I2C switch pca9548
[    4.056034] i2c i2c-1: Added multiplexed i2c bus 14
[    4.061034] i2c i2c-1: Added multiplexed i2c bus 15
[    4.066035] i2c i2c-1: Added multiplexed i2c bus 16
[    4.071041] i2c i2c-1: Added multiplexed i2c bus 17
[    4.076041] i2c i2c-1: Added multiplexed i2c bus 18
[    4.081045] i2c i2c-1: Added multiplexed i2c bus 19
[    4.086052] i2c i2c-1: Added multiplexed i2c bus 20
[    4.091067] i2c i2c-1: Added multiplexed i2c bus 21
[    4.095939] pca954x 1-0075: registered 8 multiplexed busses for I2C switch pca9548
[    4.103545] cdns-i2c ff030000.i2c: 400 kHz mmio ff030000 irq 42
[    4.113346] cdns-wdt fd4d0000.watchdog: Xilinx Watchdog Timer with timeout 60s
[    4.120815] cdns-wdt ff150000.watchdog: Xilinx Watchdog Timer with timeout 10s
[    4.130573] zynqmp-display fd4a0000.display: vtc bridge property not present
[    4.139469] xilinx-dp-snd-codec fd4a0000.display:zynqmp_dp_snd_codec0: Xilinx DisplayPort Sound Codec probed
[    4.149545] xilinx-dp-snd-pcm zynqmp_dp_snd_pcm0: Xilinx DisplayPort Sound PCM probed
[    4.157607] xilinx-dp-snd-pcm zynqmp_dp_snd_pcm1: Xilinx DisplayPort Sound PCM probed
[    4.162946] mmc0: SDHCI controller on ff170000.mmc [ff170000.mmc] using ADMA 64-bit
[    4.174046] xilinx-dp-snd-card fd4a0000.display:zynqmp_dp_snd_card: Xilinx DisplayPort Sound Card probed
[    4.183631] OF: graph: no port node found in /axi/display@fd4a0000
[    4.190151] xlnx-drm xlnx-drm.0: bound fd4a0000.display (ops 0xffff800008e649d8)
[    4.228283] mmc0: new high speed SDHC card at address 59b4
[    4.234149] mmcblk0: mmc0:59b4 LX32G 29.5 GiB
[    4.240090]  mmcblk0: p1 p2
[    5.275010] zynqmp-display fd4a0000.display: [drm] Cannot find any crtc or sizes
[    5.282670] [drm] Initialized xlnx 1.0.0 20130509 for fd4a0000.display on minor 0
[    5.290184] zynqmp-display fd4a0000.display: ZynqMP DisplayPort Subsystem driver probed
[    5.298472] ahci-ceva fd0c0000.ahci: supply ahci not found, using dummy regulator
[    5.306027] ahci-ceva fd0c0000.ahci: supply phy not found, using dummy regulator
[    5.313498] ahci-ceva fd0c0000.ahci: supply target not found, using dummy regulator
[    5.331397] ahci-ceva fd0c0000.ahci: AHCI 0001.0301 32 slots 2 ports 6 Gbps 0x3 impl platform mode
[    5.340357] ahci-ceva fd0c0000.ahci: flags: 64bit ncq sntf pm clo only pmp fbs pio slum part ccc sds apst
[    5.350836] scsi host0: ahci-ceva
[    5.354442] scsi host1: ahci-ceva
[    5.357861] ata1: SATA max UDMA/133 mmio [mem 0xfd0c0000-0xfd0c1fff] port 0x100 irq 48
[    5.365784] ata2: SATA max UDMA/133 mmio [mem 0xfd0c0000-0xfd0c1fff] port 0x180 irq 48
[    5.396587] xhci-hcd xhci-hcd.1.auto: xHCI Host Controller
[    5.402083] xhci-hcd xhci-hcd.1.auto: new USB bus registered, assigned bus number 1
[    5.409838] xhci-hcd xhci-hcd.1.auto: hcc params 0x0238f625 hci version 0x100 quirks 0x0000000002010890
[    5.419258] xhci-hcd xhci-hcd.1.auto: irq 70, io mem 0xfe200000
[    5.425392] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002, bcdDevice= 5.15
[    5.433657] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    5.440878] usb usb1: Product: xHCI Host Controller
[    5.445745] usb usb1: Manufacturer: Linux 5.15.36-xilinx-v2022.2 xhci-hcd
[    5.452525] usb usb1: SerialNumber: xhci-hcd.1.auto
[    5.457709] hub 1-0:1.0: USB hub found
[    5.461483] hub 1-0:1.0: 1 port detected
[    5.465592] xhci-hcd xhci-hcd.1.auto: xHCI Host Controller
[    5.471089] xhci-hcd xhci-hcd.1.auto: new USB bus registered, assigned bus number 2
[    5.478749] xhci-hcd xhci-hcd.1.auto: Host supports USB 3.0 SuperSpeed
[    5.485395] usb usb2: New USB device found, idVendor=1d6b, idProduct=0003, bcdDevice= 5.15
[    5.493657] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    5.500878] usb usb2: Product: xHCI Host Controller
[    5.505752] usb usb2: Manufacturer: Linux 5.15.36-xilinx-v2022.2 xhci-hcd
[    5.512534] usb usb2: SerialNumber: xhci-hcd.1.auto
[    5.517713] hub 2-0:1.0: USB hub found
[    5.521476] hub 2-0:1.0: 1 port detected
[    5.528620] input: gpio-keys as /devices/platform/gpio-keys/input/input0
[    5.535664] of_cfs_init
[    5.538112] of_cfs_init: OK
[    5.541026] clk: Not disabling unused clocks
[    5.545553] ALSA device list:
[    5.548516]   #0: DisplayPort monitor
[    5.685250] ata1: SATA link down (SStatus 0 SControl 330)
[    5.690672] ata2: SATA link down (SStatus 0 SControl 330)
[    5.721958] EXT4-fs (mmcblk0p2): mounted filesystem with ordered data mode. Opts: (null). Quota mode: none.
[    5.731723] VFS: Mounted root (ext4 filesystem) on device 179:2.
[    5.738337] devtmpfs: mounted
[    5.741809] Freeing unused kernel memory: 2176K
[    5.746392] Run /sbin/init as init process
[    6.109936] systemd[1]: System time before build time, advancing clock.
[    6.143405] systemd[1]: systemd 249.7+ running in system mode (+PAM -AUDIT -SELINUX -APPARMOR +IMA -SMACK +SECCOMP -GCRYPT -GNUTLS -OPENSSL +ACL +BLKID -CURL -ELFUTILS -FIDO2 -IDN2 -IDN -IPTC +KMOD -LIBCRYPTSETUP +LIBFDISK -PCRE2 -PWQUALITY -P11KIT -QRENCODE -BZIP2 -LZ4 -XZ -ZLIB +ZSTD +XKBCOMMON +UTMP +SYSVINIT default-hierarchy=hybrid)
[    6.173703] systemd[1]: Detected architecture arm64.

Welcome to PetaLinux 2022.2_release_S10071807 (honister)!

[    6.215583] systemd[1]: Hostname set to <zynqmp-common-20222>.
[    6.299925] systemd-sysv-generator[200]: SysV service '/etc/init.d/sendsigs' lacks a native systemd unit file. Automatically generating a unit file for compatibility. Please update package to include a native systemd unit file, in order to make it more safe and robust.
[    6.332390] systemd-sysv-generator[200]: SysV service '/etc/init.d/umountfs' lacks a native systemd unit file. Automatically generating a unit file for compatibility. Please update package to include a native systemd unit file, in order to make it more safe and robust.
[    6.357796] systemd-sysv-generator[200]: SysV service '/etc/init.d/halt' lacks a native systemd unit file. Automatically generating a unit file for compatibility. Please update package to include a native systemd unit file, in order to make it more safe and robust.
[    6.382107] systemd-sysv-generator[200]: SysV service '/etc/init.d/umountnfs.sh' lacks a native systemd unit file. Automatically generating a unit file for compatibility. Please update package to include a native systemd unit file, in order to make it more safe and robust.
[    6.383016] zynqmp-display fd4a0000.display: [drm] Cannot find any crtc or sizes
[    6.413720] systemd-sysv-generator[200]: SysV service '/etc/init.d/save-rtc.sh' lacks a native systemd unit file. Automatically generating a unit file for compatibility. Please update package to include a native systemd unit file, in order to make it more safe and robust.
[    6.438798] systemd-sysv-generator[200]: SysV service '/etc/init.d/watchdog-init' lacks a native systemd unit file. Automatically generating a unit file for compatibility. Please update package to include a native systemd unit file, in order to make it more safe and robust.
[    6.463648] systemd-sysv-generator[200]: SysV service '/etc/init.d/reboot' lacks a native systemd unit file. Automatically generating a unit file for compatibility. Please update package to include a native systemd unit file, in order to make it more safe and robust.
[    6.487421] systemd-sysv-generator[200]: SysV service '/etc/init.d/nfsserver' lacks a native systemd unit file. Automatically generating a unit file for compatibility. Please update package to include a native systemd unit file, in order to make it more safe and robust.
[    6.511488] systemd-sysv-generator[200]: SysV service '/etc/init.d/nfscommon' lacks a native systemd unit file. Automatically generating a unit file for compatibility. Please update package to include a native systemd unit file, in order to make it more safe and robust.
[    6.535510] systemd-sysv-generator[200]: SysV service '/etc/init.d/single' lacks a native systemd unit file. Automatically generating a unit file for compatibility. Please update package to include a native systemd unit file, in order to make it more safe and robust.
[    6.559438] systemd-sysv-generator[200]: SysV service '/etc/init.d/urandom' lacks a native systemd unit file. Automatically generating a unit file for compatibility. Please update package to include a native systemd unit file, in order to make it more safe and robust.
[    6.583459] systemd-sysv-generator[200]: SysV service '/etc/init.d/dropbear' lacks a native systemd unit file. Automatically generating a unit file for compatibility. Please update package to include a native systemd unit file, in order to make it more safe and robust.
[    6.607558] systemd-sysv-generator[200]: SysV service '/etc/init.d/inetd.busybox' lacks a native systemd unit file. Automatically generating a unit file for compatibility. Please update package to include a native systemd unit file, in order to make it more safe and robust.
[    6.899853] systemd[1]: Queued start job for default target Multi-User System.
[    6.907993] random: systemd: uninitialized urandom read (16 bytes read)
[    6.946007] systemd[1]: Created slice Slice /system/getty.
[  OK  ] Created slice Slice /system/getty.
[    6.967115] random: systemd: uninitialized urandom read (16 bytes read)
[    6.975053] systemd[1]: Created slice Slice /system/modprobe.
[  OK  ] Created slice Slice /system/modprobe.
[    6.995052] random: systemd: uninitialized urandom read (16 bytes read)
[    7.002904] systemd[1]: Created slice Slice /system/serial-getty.
[  OK  ] Created slice Slice /system/serial-getty.
[    7.024112] systemd[1]: Created slice User and Session Slice.
[  OK  ] Created slice User and Session Slice.
[    7.047257] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
[  OK  ] Started Dispatch Password ts to Console Directory Watch.
[    7.071191] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
[  OK  ] Started Forward Password Ruests to Wall Directory Watch.
[    7.095254] systemd[1]: Reached target Path Units.
[  OK  ] Reached target Path Units.
[    7.111089] systemd[1]: Reached target Remote File Systems.
[  OK  ] Reached target Remote File Systems.
[    7.131078] systemd[1]: Reached target Slice Units.
[  OK  ] Reached target Slice Units.
[    7.147107] systemd[1]: Reached target Swaps.
[  OK  ] Reached target Swaps.
[    7.170710] systemd[1]: Listening on RPCbind Server Activation Socket.
[  OK  ] Listening on RPCbind Server Activation Socket.
[    7.195082] systemd[1]: Reached target RPC Port Mapper.
[  OK  ] Reached target RPC Port Mapper.
[    7.216148] systemd[1]: Listening on Syslog Socket.
[  OK  ] Listening on Syslog Socket.
[    7.231232] systemd[1]: Listening on initctl Compatibility Named Pipe.
[  OK  ] Listening on initctl Compatibility Named Pipe.
[    7.255554] systemd[1]: Listening on Journal Audit Socket.
[  OK  ] Listening on Journal Audit Socket.
[    7.275277] systemd[1]: Listening on Journal Socket (/dev/log).
[  OK  ] Listening on Journal Socket (/dev/log).
[    7.295372] systemd[1]: Listening on Journal Socket.
[  OK  ] Listening on Journal Socket.
[    7.311538] systemd[1]: Listening on Network Service Netlink Socket.
[  OK  ] Listening on Network Service Netlink Socket.
[    7.335399] systemd[1]: Listening on udev Control Socket.
[  OK  ] Listening on udev Control Socket.
[    7.355274] systemd[1]: Listening on udev Kernel Socket.
[  OK  ] Listening on udev Kernel Socket.
[    7.375316] systemd[1]: Listening on User Database Manager Socket.
[  OK  ] Listening on User Database Manager Socket.
[    7.401644] systemd[1]: Mounting Huge Pages File System...
         Mounting Huge Pages File System...
[    7.421713] systemd[1]: Mounting POSIX Message Queue File System...
         Mounting POSIX Message Queue File System...
[    7.445876] systemd[1]: Mounting Kernel Debug File System...
         Mounting Kernel Debug File System...
[    7.463410] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
[    7.475482] systemd[1]: Mounting Temporary Directory /tmp...
         Mounting Temporary Directory /tmp...
[    7.492253] systemd[1]: Condition check resulted in Create List of Static Device Nodes being skipped.
[    7.504596] systemd[1]: Starting Load Kernel Module configfs...
         Starting Load Kernel Module configfs...
[    7.522313] systemd[1]: Starting Load Kernel Module drm...
         Starting Load Kernel Module drm...
[    7.542043] systemd[1]: Starting Load Kernel Module fuse...
         Starting Load Kernel Module fuse...
[    7.562135] systemd[1]: Starting RPC Bind...
         Starting RPC Bind...
[    7.575181] systemd[1]: Condition check resulted in File System Check on Root Device being skipped.
[    7.595546] systemd[1]: Starting Load Kernel Modules...
         Starting Load Kernel Modules...
[    7.613969] systemd[1]: Starting Remount Root and Kernel File Systems...
[    7.619116] dmaproxy: loading out-of-tree module taints kernel.
         Starting Remount Root and Kernel File Systems    7.628520] EXT4-fs (mmcblk0p2): re-mounted. Opts: (null). Quota mode: none.
0m...
[    7.654110] systemd[1]: Starting Coldplug All udev Devices...
         Starting Coldplug All udev Devices...
[    7.676998] systemd[1]: Started RPC Bind.
[  OK  ] Started RPC Bind.
[    7.691476] systemd[1]: Mounted Huge Pages File System.
[  OK  ] Mounted Huge Pages File System.
[    7.715404] systemd[1]: Mounted POSIX Message Queue File System.
[  OK  ] Mounted POSIX Message Queue File System.
[    7.743560] systemd[1]: Mounted Kernel Debug File System.
[  OK  ] Mounted Kernel Debug File System.
[    7.763527] systemd[1]: Mounted Temporary Directory /tmp.
[  OK  ] Mounted Temporary Directory /tmp.
[    7.783961] systemd[1]: modprobe@configfs.service: Deactivated successfully.
[    7.792332] systemd[1]: Finished Load Kernel Module configfs.
[  OK  ] Finished Load Kernel Module configfs.
[    7.816026] systemd[1]: modprobe@drm.service: Deactivated successfully.
[    7.824248] systemd[1]: Finished Load Kernel Module drm.
[  OK  ] Finished Load Kernel Module drm.
[    7.848040] systemd[1]: modprobe@fuse.service: Deactivated successfully.
[    7.855917] systemd[1]: Finished Load Kernel Module fuse.
[  OK  ] Finished Load Kernel Module fuse.
[    7.880509] systemd[1]: Finished Load Kernel Modules.
[  OK  ] Finished Load Kernel Modules.
[    7.896525] systemd[1]: Finished Remount Root and Kernel File Systems.
[  OK  ] Finished Remount Root and Kernel File Systems.
[    7.923886] systemd[1]: Mounting NFSD configuration filesystem...
         Mounting NFSD configuration filesystem...
[    7.939546] systemd[1]: Condition check resulted in FUSE Control File System being skipped.
[    7.950882] systemd[1]: Mounting Kernel Configuration File System...
         Mounting Kernel Configuration File System...
[    7.976759] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
[    7.985398] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
[    7.997874] systemd[1]: Starting Apply Kernel Variables...
         Starting Apply Kernel Variables...
         Starting Create Static Device Nodes in /dev...
[    8.039304] systemd[1]: Failed to mount NFSD configuration filesystem.
[FAILED] Failed to mount NFSD configuration filesystem.
See 'systemctl status proc-fs-nfsd.mount' for details.
[DEPEND] Dependency failed for NFS Mount Daemon.
[DEPEND] Dependency failed for NFS server and services.
[  OK  ] Mounted Kernel Configuration File System.
[  OK  ] Finished Apply Kernel Variables.
[  OK  ] Finished Create Static Device Nodes in /dev.
[  OK  ] Reached target Preparation for Local File Systems.
         Mounting /var/volatile...
[  OK  ] Started Entropy Daemon based on the HAVEGE algorithm.
         Starting Journal Service...
         Starting Rule-based Managefor Device Events and Files...
[  OK  ] Mounted /var/volatile.
         Starting Load/Save Random Seed...
[  OK  ] Reached target Local File Systems.
[  OK  ] Finished Coldplug All udev Devices.
[  OK  ] Started Journal Service.
[  OK  ] Started Rule-based Manager for Device Events and Files.
         Starting Flush Journal to Persistent Storage...
[  OK  ] Finished Flush Journal to Persistent Storage.
         Starting Create Volatile Files and Directories...
[  OK  ] Finished Create Volatile Files and Directories.
[    8.690901] zocl-drm amba_pl@0:zyxclmm_drm: IRQ index 32 not found
         Starting Network Time Synchronization...
         Starting Record System Boot/Shutdown in UTMP...
[  OK  ] Finished Record System Boot/Shutdown in UTMP.
         Mounting NFSD configuration filesystem...
         Starting Load Kernel Module fuse...
[FAILED] Failed to mount NFSD configuration filesystem.
See 'systemctl status proc-fs-nfsd.mount' for details.
[  OK  ] Finished Load Kernel Module fuse.
[  OK  ] Listening on Load/Save RF itch Status /dev/rfkill Watch.
[  OK  ] Finished Load/Save Random Seed.
[  OK  ] Started Network Time Synchronization.
[  OK  ] Created slice Slice /system/systemd-fsck.
[  OK  ] Reached target System Initialization.
[  OK  ] Started Daily Cleanup of Temporary Directories.
[  OK  ] Reached target System Time Set.
[  OK  ] Reached target Timer Units.
[  OK  ] Listening on D-Bus System Message Bus Socket.
[  OK  ] Listening on dropbear.socket.
[  OK  ] Reached target Socket Units.
[  OK  ] Reached target Basic System.
         Starting Save/Restore Sound Card State...
[  OK  ] Started Kernel Logging Service.
[  OK  ] Started System Logging Service.
[  OK  ] Started D-Bus System Message Bus.
         Starting IPv6 Packet Filtering Framework...
         Starting IPv4 Packet Filtering Framework...
         Starting LSB: NFS support for both client and server...
         Starting File System Check on /dev/mmcblk0p1...
         Starting User Login Management...
[  OK  ] Finished Save/Restore Sound Card State.
[  OK  ] Finished IPv6 Packet Filtering Framework.
[  OK  ] Finished IPv4 Packet Filtering Framework.
[  OK  ] Started LSB: NFS support for both client and server.
[  OK  ] Finished File System Check on /dev/mmcblk0p1.
[  OK  ] Reached target Preparation for Network.
[  OK  ] Reached target Sound Card.
         Mounting /run/media/mmcblk0p1...
         Starting inetd.busybox.service...
         Starting LSB: Kernel NFS server support...
         Starting Network Configuration...
[  OK  ] Mounted /run/media/mmcblk0p1.
[  OK  ] Started inetd.busybox.service.
[FAILED] Failed to start LSB: Kernel NFS server support.
See 'systemctl status nfsserver.service' for details.
[  OK  ] Started User Login Management.
[  OK  ] Started Network Configuration.
         Starting Network Name Resolution...
[  OK  ] Started Network Name Resolution.
[  OK  ] Reached target Network.
[  OK  ] Reached target Host and Network Name Lookups.
[  OK  ] Started NFS status monitor for NFSv2/3 locking..
         Starting Permit User Sessions...
         Starting Target Communication Framework agent...
[  OK  ] Finished Permit User Sessions.
[  OK  ] Started Getty on tty1.
[  OK  ] Started Serial Getty on ttyPS0.
[  OK  ] Reached target Login Prompts.
[  OK  ] Started Target Communication Framework agent.
[  OK  ] Reached target Multi-User System.
         Starting Record Runlevel Change in UTMP...
[  OK  ] Finished Record Runlevel Change in UTMP.

PetaLinux 2022.2_release_S10071807 zynqmp-common-20222 ttyPS0

zynqmp-common-20222 login: root (automatic login)

root@zynqmp-common-20222:~# ls
root@zynqmp-common-20222:~# ls /run/media/mmcblk0p1/
BOOT.BIN  Image  boot.scr  compiled_model_zcu102_B512x2.zip  dpu.xclbin  dpu_sw_optimize.tar.gz  img.tar.xz  samples.zip
root@zynqmp-common-20222:~# cp -r /run/media/mmcblk0p1/dpu_sw_optimize.tar.gz ~
root@zynqmp-common-20222:~#
root@zynqmp-common-20222:~# ls
dpu_sw_optimize.tar.gz
root@zynqmp-common-20222:~# tar -xvzf dpu_sw_optimize.tar.gz
dpu_sw_optimize/
dpu_sw_optimize/zynqmp/
dpu_sw_optimize/zynqmp/README.md
dpu_sw_optimize/zynqmp/functions/
dpu_sw_optimize/zynqmp/functions/zynqmp_qos_en.sh
dpu_sw_optimize/zynqmp/functions/ext4_auto_resize.sh
dpu_sw_optimize/zynqmp/functions/irps5401
dpu_sw_optimize/zynqmp/functions/irps5401.c
dpu_sw_optimize/zynqmp/zynqmp_dpu_optimize.sh
root@zynqmp-common-20222:~# ls
dpu_sw_optimize  dpu_sw_optimize.tar.gz
root@zynqmp-common-20222:~#
root@zynqmp-common-20222:~#
root@zynqmp-common-20222:~# cd dpu_sw_optimize/
root@zynqmp-common-20222:~/dpu_sw_optimize# ls
zynqmp
root@zynqmp-common-20222:~/dpu_sw_optimize# cd zynqmp/
root@zynqmp-common-20222:~/dpu_sw_optimize/zynqmp# ls
README.md  functions  zynqmp_dpu_optimize.sh
root@zynqmp-common-20222:~/dpu_sw_optimize/zynqmp# sudo zynqmp_dpu_optimize.sh
sudo: zynqmp_dpu_optimize.sh: command not found
root@zynqmp-common-20222:~/dpu_sw_optimize/zynqmp# sudo ./zynqmp_dpu_optimize.sh
Auto resize ext4 partition ...[?]
Start QoS config ...[?]
root@zynqmp-common-20222:~/dpu_sw_optimize/zynqmp#
root@zynqmp-common-20222:~/dpu_sw_optimize/zynqmp# df -h
Filesystem      Size  Used Avail Use% Mounted on
/dev/root        27G  1.4G   25G   6% /
devtmpfs        176M  4.0K  176M   1% /dev
tmpfs           945M     0  945M   0% /dev/shm
tmpfs           378M  9.9M  368M   3% /run
tmpfs           4.0M     0  4.0M   0% /sys/fs/cgroup
tmpfs           945M     0  945M   0% /tmp
tmpfs           945M   76K  945M   1% /var/volatile
/dev/mmcblk0p1 1016M  137M  880M  14% /run/media/mmcblk0p1
tmpfs           189M     0  189M   0% /run/user/0
root@zynqmp-common-20222:~/dpu_sw_optimize/zynqmp#
root@zynqmp-common-20222:~/dpu_sw_optimize/zynqmp#
root@zynqmp-common-20222:~/dpu_sw_optimize/zynqmp# ls
README.md  functions  zynqmp_dpu_optimize.sh
root@zynqmp-common-20222:~/dpu_sw_optimize/zynqmp# cd
root@zynqmp-common-20222:~#
root@zynqmp-common-20222:~#
root@zynqmp-common-20222:~# ls
dpu_sw_optimize  dpu_sw_optimize.tar.gz
root@zynqmp-common-20222:~# ls /run/media/mmcblk0p1/
BOOT.BIN  Image  boot.scr  compiled_model_zcu102_B512x2.zip  dpu.xclbin  dpu_sw_optimize.tar.gz  img.tar.xz  samples.zip
root@zynqmp-common-20222:~# cp -r /run/media/mmcblk0p1/samples.zip ~
root@zynqmp-common-20222:~# ls
dpu_sw_optimize  dpu_sw_optimize.tar.gz  samples.zip
root@zynqmp-common-20222:~# cp -r /run/media/mmcblk0p1/img.tar.xz ~
root@zynqmp-common-20222:~# ls
dpu_sw_optimize  dpu_sw_optimize.tar.gz  img.tar.xz  samples.zip
root@zynqmp-common-20222:~#
root@zynqmp-common-20222:~# cp -r /run/media/mmcblk0p1/compiled_model_zcu102_B512x2.zip ~
root@zynqmp-common-20222:~# ls
compiled_model_zcu102_B512x2.zip  dpu_sw_optimize  dpu_sw_optimize.tar.gz  img.tar.xz  samples.zip
root@zynqmp-common-20222:~#
root@zynqmp-common-20222:~#
root@zynqmp-common-20222:~# df -h
Filesystem      Size  Used Avail Use% Mounted on
/dev/root        27G  1.5G   25G   6% /
devtmpfs        176M  4.0K  176M   1% /dev
tmpfs           945M     0  945M   0% /dev/shm
tmpfs           378M  9.9M  368M   3% /run
tmpfs           4.0M     0  4.0M   0% /sys/fs/cgroup
tmpfs           945M     0  945M   0% /tmp
tmpfs           945M   80K  945M   1% /var/volatile
/dev/mmcblk0p1 1016M  137M  880M  14% /run/media/mmcblk0p1
tmpfs           189M     0  189M   0% /run/user/0
root@zynqmp-common-20222:~#
root@zynqmp-common-20222:~#
root@zynqmp-common-20222:~# ls
compiled_model_zcu102_B512x2.zip  dpu_sw_optimize  dpu_sw_optimize.tar.gz  img.tar.xz  samples.zip
root@zynqmp-common-20222:~# tar -xvzf img.tar.xz
tar: invalid magic
tar: short read
root@zynqmp-common-20222:~# unzip samples.zip
Archive:  samples.zip
   creating: samples/
  inflating: samples/build.sh
   creating: samples/bin/
  inflating: samples/bin/resnet50
   creating: samples/include/
   creating: samples/include/UniLog/
  inflating: samples/include/UniLog/ErrorCode.hpp
  inflating: samples/include/UniLog/UniLog.hpp
  inflating: samples/include/UniLog/UniLogExport.hpp
   creating: samples/include/vart/
  inflating: samples/include/vart/runner.hpp
  inflating: samples/include/vart/runner_ext.hpp
  inflating: samples/include/vart/softmax_runner.hpp
  inflating: samples/include/vart/softmax_runner_cpu.hpp
  inflating: samples/include/vart/tensor_buffer.hpp
  inflating: samples/include/vart/tensor_buffer_unowned_device.hpp
  inflating: samples/include/vart/tensor_mirror_attrs.hpp
  inflating: samples/include/vart/util_4bit.hpp
  inflating: samples/include/vart/util_export.hpp
  inflating: samples/include/vart/xir_helper.hpp
  inflating: samples/include/vart/zero_copy_helper.hpp
   creating: samples/include/vart/assistant/
  inflating: samples/include/vart/assistant/batch_tensor_buffer.hpp
  inflating: samples/include/vart/assistant/tensor_buffer_allocator.hpp
  inflating: samples/include/vart/assistant/xrt_bo_tensor_buffer.hpp
   creating: samples/include/vart/dpu/
  inflating: samples/include/vart/dpu/vitis_dpu_runner_factory.hpp
   creating: samples/include/vart/experimental/
  inflating: samples/include/vart/experimental/runner_helper.hpp
   creating: samples/include/vart/mm/
  inflating: samples/include/vart/mm/host_flat_tensor_buffer.hpp
   creating: samples/include/vart/trace/
  inflating: samples/include/vart/trace/common.hpp
  inflating: samples/include/vart/trace/event.hpp
  inflating: samples/include/vart/trace/fmt.hpp
  inflating: samples/include/vart/trace/payload.hpp
  inflating: samples/include/vart/trace/ringbuf.hpp
  inflating: samples/include/vart/trace/trace.hpp
  inflating: samples/include/vart/trace/traceclass.hpp
  inflating: samples/include/vart/trace/vaitrace_dbg.hpp
   creating: samples/include/vart/tracelogging/
  inflating: samples/include/vart/tracelogging/tracelogging.hpp
   creating: samples/include/vitis/
   creating: samples/include/vitis/ai/
  inflating: samples/include/vitis/ai/bounded_queue.hpp
  inflating: samples/include/vitis/ai/c++14.hpp
  inflating: samples/include/vitis/ai/collection_helper.hpp
  inflating: samples/include/vitis/ai/dim_calc.hpp
  inflating: samples/include/vitis/ai/dpu_runner.hpp
  inflating: samples/include/vitis/ai/env_config.hpp
  inflating: samples/include/vitis/ai/erl_msg_box.hpp
  inflating: samples/include/vitis/ai/linked_list_queue.hpp
  inflating: samples/include/vitis/ai/lock.hpp
  inflating: samples/include/vitis/ai/nocopy_bounded_queue.hpp
  inflating: samples/include/vitis/ai/parse_value.hpp
  inflating: samples/include/vitis/ai/performance_test.hpp
  inflating: samples/include/vitis/ai/plugin.hpp
  inflating: samples/include/vitis/ai/profiling.hpp
  inflating: samples/include/vitis/ai/ring_queue.hpp
  inflating: samples/include/vitis/ai/runner.hpp
  inflating: samples/include/vitis/ai/shared_queue.hpp
  inflating: samples/include/vitis/ai/simple_config.hpp
  inflating: samples/include/vitis/ai/sorted_queue.hpp
  inflating: samples/include/vitis/ai/target.pb.h
  inflating: samples/include/vitis/ai/target_factory.hpp
  inflating: samples/include/vitis/ai/tensor.hpp
  inflating: samples/include/vitis/ai/tensor_buffer.hpp
  inflating: samples/include/vitis/ai/thread_pool.hpp
  inflating: samples/include/vitis/ai/time_measure.hpp
  inflating: samples/include/vitis/ai/tracelogging.hpp
  inflating: samples/include/vitis/ai/util_export.hpp
  inflating: samples/include/vitis/ai/variable_bit.hpp
  inflating: samples/include/vitis/ai/weak.hpp
  inflating: samples/include/vitis/ai/with_injection.hpp
  inflating: samples/include/vitis/ai/xxd.hpp
   creating: samples/include/vitis/ai/library/
  inflating: samples/include/vitis/ai/library/tensor.hpp
   creating: samples/include/xir/
  inflating: samples/include/xir/XirExport.hpp
  inflating: samples/include/xir/buffer_object.hpp
  inflating: samples/include/xir/device_memory.hpp
  inflating: samples/include/xir/dpu_controller.hpp
  inflating: samples/include/xir/sfm_controller.hpp
  inflating: samples/include/xir/xrt_device_handle.hpp
   creating: samples/include/xir/attrs/
  inflating: samples/include/xir/attrs/attr_def.hpp
  inflating: samples/include/xir/attrs/attr_expander.hpp
  inflating: samples/include/xir/attrs/attrs.hpp
   creating: samples/include/xir/graph/
  inflating: samples/include/xir/graph/graph.hpp
  inflating: samples/include/xir/graph/graph_template.hpp
  inflating: samples/include/xir/graph/subgraph.hpp
   creating: samples/include/xir/op/
  inflating: samples/include/xir/op/op.hpp
  inflating: samples/include/xir/op/op_def.hpp
   creating: samples/include/xir/tensor/
  inflating: samples/include/xir/tensor/tensor.hpp
   creating: samples/include/xir/util/
  inflating: samples/include/xir/util/any.hpp
  inflating: samples/include/xir/util/data_type.hpp
  inflating: samples/include/xir/util/tool_function.hpp
   creating: samples/lib/
    linking: samples/lib/libunilog.so  -> libunilog.so.3
    linking: samples/lib/libunilog.so.3  -> libunilog.so.3.0.0
  inflating: samples/lib/libunilog.so.3.0.0
    linking: samples/lib/libvart-buffer-object.so  -> libvart-buffer-object.so.3
    linking: samples/lib/libvart-buffer-object.so.3  -> libvart-buffer-object.so.3.0.0
  inflating: samples/lib/libvart-buffer-object.so.3.0.0
    linking: samples/lib/libvart-dpu-controller.so  -> libvart-dpu-controller.so.3
    linking: samples/lib/libvart-dpu-controller.so.3  -> libvart-dpu-controller.so.3.0.0
  inflating: samples/lib/libvart-dpu-controller.so.3.0.0
    linking: samples/lib/libvart-dpu-runner.so  -> libvart-dpu-runner.so.3
    linking: samples/lib/libvart-dpu-runner.so.3  -> libvart-dpu-runner.so.3.0.0
  inflating: samples/lib/libvart-dpu-runner.so.3.0.0
    linking: samples/lib/libvart-mem-manager.so  -> libvart-mem-manager.so.3
    linking: samples/lib/libvart-mem-manager.so.3  -> libvart-mem-manager.so.3.0.0
  inflating: samples/lib/libvart-mem-manager.so.3.0.0
    linking: samples/lib/libvart-runner-assistant.so  -> libvart-runner-assistant.so.3
    linking: samples/lib/libvart-runner-assistant.so.3  -> libvart-runner-assistant.so.3.0.0
  inflating: samples/lib/libvart-runner-assistant.so.3.0.0
    linking: samples/lib/libvart-runner.so  -> libvart-runner.so.3
    linking: samples/lib/libvart-runner.so.3  -> libvart-runner.so.3.0.0
  inflating: samples/lib/libvart-runner.so.3.0.0
    linking: samples/lib/libvart-trace.so  -> libvart-trace.so.3
    linking: samples/lib/libvart-trace.so.3  -> libvart-trace.so.3.0.0
  inflating: samples/lib/libvart-trace.so.3.0.0
    linking: samples/lib/libvart-util.so  -> libvart-util.so.3
    linking: samples/lib/libvart-util.so.3  -> libvart-util.so.3.0.0
  inflating: samples/lib/libvart-util.so.3.0.0
    linking: samples/lib/libvart-xrt-device-handle.so  -> libvart-xrt-device-handle.so.3
    linking: samples/lib/libvart-xrt-device-handle.so.3  -> libvart-xrt-device-handle.so.3.0.0
  inflating: samples/lib/libvart-xrt-device-handle.so.3.0.0
    linking: samples/lib/libxir.so   -> libxir.so.3
    linking: samples/lib/libxir.so.3  -> libxir.so.3.0.0
  inflating: samples/lib/libxir.so.3.0.0
   creating: samples/src/
  inflating: samples/src/resnet50.cpp
  inflating: samples/src/word_list.inc
finishing deferred symbolic links:
  samples/lib/libunilog.so -> libunilog.so.3
  samples/lib/libunilog.so.3 -> libunilog.so.3.0.0
  samples/lib/libvart-buffer-object.so -> libvart-buffer-object.so.3
  samples/lib/libvart-buffer-object.so.3 -> libvart-buffer-object.so.3.0.0
  samples/lib/libvart-dpu-controller.so -> libvart-dpu-controller.so.3
  samples/lib/libvart-dpu-controller.so.3 -> libvart-dpu-controller.so.3.0.0
  samples/lib/libvart-dpu-runner.so -> libvart-dpu-runner.so.3
  samples/lib/libvart-dpu-runner.so.3 -> libvart-dpu-runner.so.3.0.0
  samples/lib/libvart-mem-manager.so -> libvart-mem-manager.so.3
  samples/lib/libvart-mem-manager.so.3 -> libvart-mem-manager.so.3.0.0
  samples/lib/libvart-runner-assistant.so -> libvart-runner-assistant.so.3
  samples/lib/libvart-runner-assistant.so.3 -> libvart-runner-assistant.so.3.0.0
  samples/lib/libvart-runner.so -> libvart-runner.so.3
  samples/lib/libvart-runner.so.3 -> libvart-runner.so.3.0.0
  samples/lib/libvart-trace.so -> libvart-trace.so.3
  samples/lib/libvart-trace.so.3 -> libvart-trace.so.3.0.0
  samples/lib/libvart-util.so -> libvart-util.so.3
  samples/lib/libvart-util.so.3 -> libvart-util.so.3.0.0
  samples/lib/libvart-xrt-device-handle.so -> libvart-xrt-device-handle.so.3
  samples/lib/libvart-xrt-device-handle.so.3 -> libvart-xrt-device-handle.so.3.0.0
  samples/lib/libxir.so  -> libxir.so.3
  samples/lib/libxir.so.3 -> libxir.so.3.0.0
root@zynqmp-common-20222:~#
root@zynqmp-common-20222:~#
root@zynqmp-common-20222:~# ls
compiled_model_zcu102_B512x2.zip  dpu_sw_optimize  dpu_sw_optimize.tar.gz  img.tar.xz  samples  samples.zip
root@zynqmp-common-20222:~# tar -xf img.tar.xz
root@zynqmp-common-20222:~# ls
compiled_model_zcu102_B512x2.zip  dpu_sw_optimize  dpu_sw_optimize.tar.gz  img  img.tar.xz  samples  samples.zip
root@zynqmp-common-20222:~# unzip compiled_model_zcu102_B512x2.zip
Archive:  compiled_model_zcu102_B512x2.zip
   creating: compiled_model_zcu102_B512x2/
  inflating: compiled_model_zcu102_B512x2/meta.json
  inflating: compiled_model_zcu102_B512x2/tf_resnet50.xmodel
  inflating: compiled_model_zcu102_B512x2/md5sum.txt
  inflating: compiled_model_zcu102_B512x2/resnet50.xmodel
root@zynqmp-common-20222:~# ls
compiled_model_zcu102_B512x2  compiled_model_zcu102_B512x2.zip  dpu_sw_optimize  dpu_sw_optimize.tar.gz  img  img.tar.xz  samples  samples.zip
root@zynqmp-common-20222:~# cp -r compiled_model_zcu102_B512x2/resnet50.xmodel ~
root@zynqmp-common-20222:~# ls
compiled_model_zcu102_B512x2  compiled_model_zcu102_B512x2.zip  dpu_sw_optimize  dpu_sw_optimize.tar.gz  img  img.tar.xz  resnet50.xmodel  samples  samples.zip
root@zynqmp-common-20222:~# env LD_LIBRARY_PATH=samples/lib XLNX_VART_FIRMWARE=/run/media/mmcblk0p1/dpu.xclbin samples/bin/resnet50 img/bellpeppe-994958.JPEG
score[945]  =  0.990914     text: bell pepper,
score[941]  =  0.00857309   text: acorn squash,
score[943]  =  0.00020162   text: cucumber, cuke,
score[939]  =  4.49874e-05  text: zucchini, courgette,
score[679]  =  4.49874e-05  text: necklace,
root@zynqmp-common-20222:~#
root@zynqmp-common-20222:~#
root@zynqmp-common-20222:~# env LD_LIBRARY_PATH=samples/lib XLNX_VART_FIRMWARE=/run/media/mmcblk0p1/dpu.xclbin samples/bin/resnet50 img/greyfox-672194.JPEG
score[280]  =  0.917925     text: grey fox, gray fox, Urocyon cinereoargenteus,
score[272]  =  0.0277189    text: coyote, prairie wolf, brush wolf, Canis latrans,
score[277]  =  0.0277189    text: red fox, Vulpes vulpes,
score[279]  =  0.00618493   text: Arctic fox, white fox, Alopex lagopus,
score[269]  =  0.00618493   text: timber wolf, grey wolf, gray wolf, Canis lupus,
root@zynqmp-common-20222:~#
root@zynqmp-common-20222:~#
root@zynqmp-common-20222:~# env LD_LIBRARY_PATH=samples/lib XLNX_VART_FIRMWARE=/run/media/mmcblk0p1/dpu.xclbin samples/bin/resnet50 img/jinrikisha-911722.JPEG
score[870]  =  0.880801     text: tricycle, trike, velocipede,
score[513]  =  0.0563077    text: cornet, horn, trumpet, trump,
score[566]  =  0.0265979    text: French horn, horn,
score[612]  =  0.00978482   text: jinrikisha, ricksha, rickshaw,
score[776]  =  0.00462202   text: sax, saxophone,
root@zynqmp-common-20222:~#
root@zynqmp-common-20222:~#
root@zynqmp-common-20222:~# env LD_LIBRARY_PATH=samples/lib XLNX_VART_FIRMWARE=/run/media/mmcblk0p1/dpu.xclbin samples/bin/resnet50 img/irishterrier-696543.JPEG
score[252]  =  0.188241     text: affenpinscher, monkey pinscher, monkey dog,
score[197]  =  0.188241     text: giant schnauzer,
score[184]  =  0.146602     text: Irish terrier,
score[262]  =  0.114174     text: Brabancon griffon,
score[170]  =  0.0889188    text: Irish wolfhound,
root@zynqmp-common-20222:~#
root@zynqmp-common-20222:~#
root@zynqmp-common-20222:~#
root@zynqmp-common-20222:~# lsmod
Module                  Size  Used by
zocl                  184320  0
mali                  229376  0
uio_pdrv_genirq        16384  0
dmaproxy               16384  0
root@zynqmp-common-20222:~#
root@zynqmp-common-20222:~#
root@zynqmp-common-20222:~#
root@zynqmp-common-20222:~#
root@zynqmp-common-20222:~#
root@zynqmp-common-20222:~# dmesg
[    0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
[    0.000000] Linux version 5.15.36-xilinx-v2022.2 (oe-user@oe-host) (aarch64-xilinx-linux-gcc (GCC) 11.2.0, GNU ld (GNU Binutils) 2.37.20210721) #1 SMP Mon Oct 3 07:50:07 UTC 2022
[    0.000000] Machine model: ZynqMP ZCU102 Rev1.0
[    0.000000] earlycon: cdns0 at MMIO 0x00000000ff000000 (options '115200n8')
[    0.000000] printk: bootconsole [cdns0] enabled
[    0.000000] efi: UEFI not found.
[    0.000000] Zone ranges:
[    0.000000]   DMA32    [mem 0x0000000000000000-0x00000000ffffffff]
[    0.000000]   Normal   [mem 0x0000000100000000-0x000000087fffffff]
[    0.000000] Movable zone start for each node
[    0.000000] Early memory node ranges
[    0.000000]   node   0: [mem 0x0000000000000000-0x000000007fefffff]
[    0.000000]   node   0: [mem 0x0000000800000000-0x000000087fffffff]
[    0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x000000087fffffff]
[    0.000000] On node 0, zone Normal: 256 pages in unavailable ranges
[    0.000000] cma: Reserved 1536 MiB at 0x0000000017800000
[    0.000000] psci: probing for conduit method from DT.
[    0.000000] psci: PSCIv1.1 detected in firmware.
[    0.000000] psci: Using standard PSCI v0.2 function IDs
[    0.000000] psci: MIGRATE_INFO_TYPE not supported.
[    0.000000] psci: SMC Calling Convention v1.2
[    0.000000] percpu: Embedded 18 pages/cpu s34776 r8192 d30760 u73728
[    0.000000] pcpu-alloc: s34776 r8192 d30760 u73728 alloc=18*4096
[    0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3
[    0.000000] Detected VIPT I-cache on CPU0
...

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Credits

LogicTronix [FPGA Design + Machine Learning Company]

43 projects • 170 followers

We are Certified FPGA Design + Machine Learning Company with expertise on Machine Learning, Computer Vision, Embedded & Crypto Development.

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ZCU102-Vitis DPU TRD - Vitis AI (3.0)

Things used in this project

Hardware components

Software apps and online services

Story

A. Base Platform and ZYNQMP common image for ZCU102

B. Building the Hardware Overlay

C. Booting the ZCU102

D. Compiling the Resnet50 Model as of DPU Architecture

E. Running the Demo

F. Debug Points or Hints on Vitis DPU TRD with ZCU102 or Custom Board

G. Common issues and solutions from Xilinx Forum and Git-Issues

H. Conclusion

Code

Vitis_DPU_TRD_ZCU102_Build_LOG_M2023.sh

Vitis_AI_Compilation_log_tf_Resnet50.sh

ZCU102_Vitis_DPU_TRD_3_0_BOOT_LOG.sh

Credits

LogicTronix [FPGA Design + Machine Learning Company]

Comments

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ZCU102-Vitis DPU TRD - Vitis AI (3.0)

ZCU102-Vitis DPU TRD - Vitis AI (3.0)

Things used in this project

Hardware components

Software apps and online services

Story

A. Base Platform and ZYNQMP common image for ZCU102

B. Building the Hardware Overlay

C. Booting the ZCU102

D. Compiling the Resnet50 Model as of DPU Architecture

E. Running the Demo

F. Debug Points or Hints on Vitis DPU TRD with ZCU102 or Custom Board

G. Common issues and solutions from Xilinx Forum and Git-Issues

H. Conclusion

Code

Vitis_DPU_TRD_ZCU102_Build_LOG_M2023.sh

Vitis_AI_Compilation_log_tf_Resnet50.sh

ZCU102_Vitis_DPU_TRD_3_0_BOOT_LOG.sh

Credits

LogicTronix [FPGA Design + Machine Learning Company]

Comments

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