Dual Address Cosine ROM Using Verilog in Vivado

module COSINE_ROM (clk, addr1, addr2, dout1, dout2);
    input clk; 
    input [2:0]addr1; 
    input [2:0]addr2;
    output [63:0] dout1;   //64 bit data out
    output [63:0] dout2;   //64 bit data out
  
    reg [63:0] r1;
    reg [63:0] r2;
    reg [63:0] pr1;   // first pipeline register 
    reg [63:0] pr2;   // second pipeline register
    reg [63:0] dout1;
    reg [63:0] dout2;

    wire [63:0] loc0;   //declaration of ROM data as nets
    wire [63:0] loc1;
    wire [63:0] loc2;
    wire [63:0] loc3;
    wire [63:0] loc4;
    wire [63:0] loc5;
    wire [63:0] loc6;
    wire [63:0] loc7;
  
    assign loc0 = 64'hA3A3A3A3A3A3A3A3;     //ROM data of 8 numbers having 8 bit data per location
    assign loc1 = 64'hAE5388B3568ED75D;
    assign loc2 = 64'hB48A58E49B447C02;
    assign loc3 = 64'hA7329B2092E399DA;
    assign loc4 = 64'hD7852398C002B27A;
    assign loc5 = 64'hE821B5490C12398E;
    assign loc6 = 64'hE757B8CA809B19AE;
    assign loc7 = 64'h6A7B459D001A496D;

    always@(loc0 or loc1 or loc2 or loc3 or loc4 or loc5 or loc6 or loc7 or addr1 or addr2)
    begin
       case (addr1)            //addr1 serves as address to read data
         3'b000: r1 = loc0;
         3'b001: r1 = loc1;
         3'b010: r1 = loc2;
         3'b011: r1 = loc3;
         3'b100: r1 = loc4;
         3'b101: r1 = loc5;
         3'b110: r1 = loc6;
         3'b111: r1 = loc7;
         default: r1 = loc0;
       endcase
       case (addr2)            //addr2 serves as address to read data
         3'b000: r2 = loc0;
         3'b001: r2 = loc1;
         3'b010: r2 = loc2;
         3'b011: r2 = loc3;
         3'b100: r2 = loc4;
         3'b101: r2 = loc5;
         3'b110: r2 = loc6;
         3'b111: r2 = loc7;
         default: r2 = loc0;
         endcase
    end

    always@(posedge clk)  //first pipelining stage
    begin
        pr1 <= r1;
        pr2 <= r2;
    end

    always@(posedge clk)  //second pipelining stage
    begin
        dout1 <= pr1;
        dout2 <= pr2;
    end

endmodule