A beginner's guide to the STM32

Story:

This article comes from my attempt to replicate a Flipper Zero, which took a lot of research and documentation. My goal in sharing this is to create a go-to guide with all the key info you need to get a basic understanding of how to use the STM32.

Keep in mind that as this documentation was written by me some information may not be correct. Please feel free to send me a message if you find any mistakes. Additionally, this does not delve into how to program the STM32.

MCU STM32WB55 MCU (Microcontroller Unit)

The STM32WB55 is a highly capable embedded multiprotocol wireless device known for its ultra-low-power consumption. It features a dedicated Arm Cortex-M0+ core, which handles real-time low-level operations (The processing of data at the earliest stages of a system, where latency and predictability are crucial). The Cortex-M0+ architecture is specifically designed for energy-efficient, resource-constrained embedded applications.

The STM32WB55 operates at a frequency of up to 64 MHz and is based on a 32-bit RISC architecture. It includes a single-precision Floating Point Unit (FPU) that supports all Arm single-precision data-processing instructions and data types. Additionally, it comes equipped with a comprehensive set of DSP instructions and a Memory Protection Unit (MPU) to enhance application security.

General Specifications

• Up to 1 Mbyte of flash memory for the STM32WB55xx, up to 512 Kbytes for STM32WB35xx
• Up to 256 Kbytes of SRAM (Static Random Access Memory) for STM32WB55xx and 96 Kbytes for STM32WB35xx
• Quad-SPI (Serial Peripheral Interface) flash memory interface; A high speed, low-pin-count serial interface used for communication between a microcontroller and flash memory chips.
• Extensive range of enhance I/Os and peripherals
• Direct data transfer between memory and peripherals and from memory to memory is supported by fourteen DMA channels.
• Two AES encryption engines, PKA, and RNG enable lower layer MAC and upper layer cryptography
• Offers a fast 12-bit ADC 4.26 Msps
• Two ultra-low-power comparators associated with a high accuracy reference voltage generator.
• 18 capacitive sensing channels
• STM32WB55xx embeds an integrated LCD driver up to 8x40 or 4x44
• Feature standard and advanced communication interfaces, namely one USART, one low-power UART, two I2Cs, two SPIs up to 32 MHz, one serial audio interface with two channels and three PDMs.
• Device includes independent power supplies for analog input for ADC.
• 3.3V dedicated power supply input for USB.
• Accurate 2.5 V or 2.048 V reference voltage buffered output

Radio Specifications

• 2.4GHz
• RF transceiver supporting Bluetooth 5.4
• RX sensitivity
• Programmable output up to +6 dBm with 1dB steps
• Integrated balun to reduce BOM
• Support for 2Mbps

STM32 Terminology:

Peripheral devices: A peripheral device is an external hardware component that connects to a computer system to expand its capabilities. It is not essential to the functioning of a computer, but enhances it functionality.

LDO: The LDO (Low-Dropout) regulator integrated into the STM32 is a linear voltage regulator designed to provide a stable and regulated output voltage to the internal circuits, even when the input voltage fluctuates.

Unlike standard regulators, an LDO can operate with a minimal difference—just a few hundred millivolts—between the input and output voltages, making it ideal for battery-powered applications. LDOs are highly efficient, requiring very low quiescent current, which means they consume minimal power when the output is not loaded. Additionally, they effectively reject noise and ripple from the input voltage, delivering a clean and stable output while also responding quickly to changes in output current demand.

SMPS: SMPS (Switched-Mode Power Supply) is an integrated power supply module that provides a regulated voltage output in the STM32. This voltage regulator uses a switching converter topology to regulate the output voltage, offering high efficiency and low quiescent current. Integrating this into the circuit eliminates the need for an external power supply module.

The SMPS provides a regulated output voltage ranging from 1.8V to 3.3V, depending on the configuration. Additionally, the SMPS can be configured to operate in different modes, such as low-power mode, high-power mode, or bypass mode. Bypass mode allows the SMPS to be bypassed (the current continues to flow through its coil)

The efficiency increases when the difference between VFBSMPS and VDD is high. To prevent the SMPS from disturbing RF performance, the switching frequency of this SMPS is synchronous with the RF main clock source. The allowed frequencies are 4 or 8 MHz.

Fm+ (Fast Mode Plus): Enables faster data transfer rates over the I2C bus. 1 Mbit/s

Fm (Fast Mode): Enables fast data transfer rates over the I2C bus of 400 kbit/s.

Sm (Standard-Mode): Standard data transfer rate over the I2C bus of 100 kbit/s.

RTC (Real Time Clock): An independent binary-coded decimal timer/counter that provides a time-of-day clock/calendar with programmable alarm interrupt.

To utilise the RTC, you need to:

Configure an external clock source and calibrate the RTC using the sub second shift feature and digital calibration circuit. Additionally, the time and date needs to be set using the RTC registers. The RTC can be configured to also enable alarm interrupts (Wakeup, Time-stamp, or Tamper detection) and configure their masking.

EVENTOUT: The majority use case for the EVENTOUT function seems to be as a power management feature for multi-processor systems. What it essentially does is wake up other processors through their respective EVENTIN signals.

USART: USART (Universal Synchronous/Asynchronous Receiver/Transmitter) is a serial interface module that can be programmed to communicate asynchronously or synchronously. In Asynchronous mode USART can transmit and receive serial data asynchronously, without the need for a shared clock. In Synchronous mode the USART module can generate a clock signal to synchronize data transmissions and receptions.

The STM32 has one embedded USART module. Its interface provides asynchronous communication and has a LIN Master/Slave capability. It is able to communicate at speeds of up to 4Mbit/s, and also provides SPI-like communication capability. Because the USART module can also go into a synchronous mode, it has an SPI mode, and can be used as an SPI master. It also has a clock domain independent from the CPU clock, allowing it to wake up the MCU (Microcontroller Unit) from Stop mode using baud rates up to 200kbaud.

USART1_RX (PA10, PB7): Used for receiving asynchronous serial data. The USART1_RX pin is an input pin, meaning it receives data from an external serial device. To use this alternate function of a GPIO pin that supports it, it needs to be configured using the STM32’s pin configuration registers.

USART1_TX (PA9, PB6): Used for transmitting asynchronous serial data. The USART1_TX pin is an output pin, meaning it transmits data to an external serial device. To use this alternate function of a GPIO pin that supports it, it needs to be configured using the STM32’s pin configuration registers.

USART1_CK (PA8): Used during Synchronous mode of the USART protocol and outputs the corresponding clock pulses for the USART transmitter. This is essential for master-mode bidirectional synchronous serial communication.

UART: UART (Universal Asynchronous Receiver Transmitter) is similar to the USART, it just lacks the ability to communicate synchronously.

I2C: The I2C (Inter-integrated Circuit) interface is a two-wire serial communication protocol used for communication between devices. I2C pins can be selected for an alternate function for the I2C pins in the GPIO configuration registers (GPIO_MODER and GPIO_AFRL). This will configure the pins for I2C communication. There are 3 I2C modules on the STM32.

I2C1/2/3_SCL (PA9, PB8, PB6, PB10.. etc): SCL refers to Synchronous Clock of the I2C1 interface. This line is used for bidirectional communication between the microcontroller and peripheral devices. This pin in particular carries the clock information from the I2C master (typical the STM32 itself) to the I2C slave devices such as peripherals connected to the I2C bus.

This pin has the following characteristics:

• ·Active high: The clock signal is high when the master is transmitting and low when the master is receiving data.
• Open-drain output: The STM32’s peripheral drives the SCL signal low, but it doesn’t provide a pull-up resistor. This means that an external pull-up resistor is required to keep the signal high when the STM32 is not driving it
• Input to I2C slaves: I2C slaves only input the SCL signal and do not drive it. They respond to the clock signal by sampling the data on the SDA line at the rising edge of the SCL. In simpler terms, the slaves respond to the clock by transmitting data on the SDA lines when high.
• Ensure that the SCL line is properly connected to the I2C slaves and that the connections are not noisy or noisy inducing. Make sure to verify that the I2C bus frequency is compatible with the requirements of the I2C slaves.

I2C1/2/3_SDA (PA10, PB9, PB7.. etc): SDA refers to Serial Data Line, on which the master and slave send or receive data on the I2C bus interface. It is a bidirectional line, connected to a positive supply voltage via a current-source or pull-up resistor.

To manually ser the I2C1_SDA pin to a low or high state, you would need to configure the pin as a general-purpose output (GPIO) and then toggle its state using the HAL library’s GPIO functions (e.g., HAL_GPIO_WritePin(GPIO0B, GPIO_PIN_9, GPIO_PIN_RESET) to set the pin low).

IR_OUT(PB9):Can’t find much data on it, seems to be an output pin for a infrared components.

SPI (Serial Peripheral Interface): On the STM32 there are two SPI interfaces which enable communication up to 32 Mbit/s in master and up to 24Mbit/s in slave modes, in half-duplex, full-duplex and simplex modes. The SPI interface operates on only one data line, and the MISO (Master In Slave Out) and MOSI (Master Out Slave In) are each respectively responsible for receiving and transmitting data. The SPI protocol also requires a SCK pin to be connected to the slave device so that the communication can be in sync with the master chip.

QuadSPI (Quad Serial Peripheral Interface): The Quad Serial Peripheral Interface (Quad-SPI) differs from the standard SPI protocol by providing four bidirectional data lines (IO0, IO1, IO2, IO3) for communication, rather than a single dedicated data line. In this configuration, the traditional MISO and MOSI pins are not needed because each of the four lines can be configured to either transmit or receive data, depending on the phase of communication. This allows for faster data transfer and greater flexibility compared to the standard SPI.

The Quad-SPI on the STM32 supports traditional SPI and dual-SPI modes, allowing communication over two or four data lines. It is a specialized interface designed specifically for interacting with single, dual, or quad SPI Flash memories. The Quad-SPI interface supports a plethora of things, but relevant to this documentation it supports both Single Data Rate (SDR) and Double Data Rate (DDR) modes, offering flexibility and enhanced performance in data transfer.

Comparator:

COMP1/2_INP (Comparator 1/2, Input Plus)

COMP1/2_INP (Comparator 1/2, Input Minus)

The comparator has two analog inputs, comparing them to generate a signal that can be routed back to a GPIO, timers, interrupts etc. The output goes high when the INP voltage is greater than the INM voltage.

Circuit Diagram:

Chip Pinout:

1. VBAT (Voltage Battery): A power supply pin that receives power from a backup power source, such as a battery. The VBAT pin is designed to provide a stable power supply to certain components or circuits within the microcontroller, even if the primary power supply is not available. In the absence of an external battery, the VBAT pin is typically connected to the VDD pin. Maximum operating voltage: 3.6V.

2. PC 13: I/O pin, 5V tolerant. Functions as an RTC alarm output as well. An RTC alarm output is a feature that enables interruptions and wake-up of a device from a low-power state. This alarm is triggered when the current time matches the set alarm time. Can additionally be configured as a WKUP2 pin.

3. PC 14-OSC32_IN: I/O pin, 5V tolerant. OSC32 input pin is used for connecting an external 32 kHz crystal oscillator (Excitation pin), which is used as a low-speed clock source for the microcontroller. This stable clock signal can be used for RTC functionality, Low-power wake-up intervals and other low-frequency operations. If clock/time/date not needed, just use the pin as I/O.

4. PC 15-OSC32_OUT: I/O pin, 5V tolerant. OSC32 output pin is used to connect the second (Feedback) pin of the 32kHz oscillator to the chip, receiving the oscillating signal from the crystal and feeding it back into the circuit, creating a close-looped feedback network.

5. PH3-BOOT0:I/O pin, 5V tolerant. This pin, BOOT0, must be pulled up (10k resistor for example) and set to 0 to boot from the Main Flash memory. To boot from System memory or Embedded SRAM, pull this pin down (low resistance resistor) and set it to 1. For System memory BOOT1 should be pulled up, for Embedded SRAM, BOOT1 should be pulled down. From Main Flash memory and BOOT1 should not be connected.

6. PB8: I/O pin, 5V tolerant. Fm+ capable and has LCD function supplied by VLCD. I2C1_SCL.

7. PB9: I/O pin, 5V tolerant. Fm+ capable and has LCD function supplied by Vlcd. Additionally possesses Analog switch function supplied by VDDA. (VDDA is the analog supply voltage for STM32 microcontrollers). I2C1_SDA, IR_OUT.

8. NRST: This is a RST pin for the chip. Activating this pin initiates a system reset which sets all registers to their reset values except for the reset flags in the clock controller CSR register and the registers in the Backup domain. This pin is usally connected to a Pull-Up resistor and set to a state of 1. This pin can be externally reset by applying a low level; connecting it to ground.

9. PC0: I/O pin, 5V tolerant. Fm+ capable, has LCD function supplied by Vlcd and possesses Analog switch function supplied by VDDA. Additionally, this pin can generate an interrupt when its state changes (rising, falling, or both) and by default is set to a Pull-down Mode, meaning that it will always read as 0, unless an external signal pulls it high. This pin can also act as an analog input for the ADC1 channel, by being configured in the STM32’s GPIO peripheral; ADC1_IN1.

10. PC1: Same as PC0, but a second configurable input for the ADC1 channel. ADC1_IN2 pin.

11. PC2: Same as PC0, but a third configurable input for the ADC1 channel. ADC1_IN3 pin.

12. PC3: Same as PC0, but a fourth configurable input for the ADC1 channel. ADC1_IN4 pin.

13. VREF+: Supply pin. This pin is an internal analog voltage reference buffer. It generates a fixed voltage reference, typically 1.21V based on an internal bandgap reference. This buffer is used as a stable reference voltage for the ADC. The math that converts the raw ADC value to a voltage relies on knowing this reference voltage, and if this were to come from the battery, it would be subject to voltage fluctuations as the battery discharges. The VREF+ pin can be connected to the VDDA external power supply through a resistor. If a separate, external reference voltage is applied to the VREF+ a 100 nF and a 1uF capacitors must be connected on this pin. In all cases, the voltage supply to this pin must be kept between (VDDA -1.2V) and a minimum of 1.7 V.

14. VDDA: Supply pin. This pin is an analog supply and analog ground pin for the MCU, powering only the analog components such as the ADC inside. The VDDA pin must be connected to two external decoupling capacitors (100nF Ceramic + 1uF Tantalum or Ceramic) and connected to the same power supply as the VDD. It can be connected to VDD through a ferrite bead. The analog and digital supplies are separated so that digital noise does not interfere with the analog supply, keeping it clean and reducing the amount of noise that could affect the ADC reading. 2.4V to 3.6V.

15. PA0: I/O pin, 5V tolerant. Analog switch function supplied by VDDA. Can be configured to work as a ADC1_IN5 pin.

16. PA1: I/O pin, 5V tolerant. Analog switch function supplied by VDDA and LCD function supplied by VLCD. Can be configured to work as a ADC1_IN6 and COMP1_INP pin.

17. PA2: Same functions as PA1. Can be configured to work as a ADC1_IN7, COMP2_INM and WKUP4 pin.

18. PA3: Same functions as PA1. Can be configured to work as a ADC1_IN8 and COMP2_INP.

19. PA4: Same functions as PA0. Can be configured to work as a ADC1_IN9 and COMP1/2_INM.

20. PA5: Same functions as PA0. Can be configured to work as a ADC1_IN10 and COMP1/2_INM.

21. PA6: Same functions as PA1. Can be configured to work as a ADC1_IN11.

22. PA7: I/O pin, 5V tolerant. Analog switch function supplied by VDDA, Fm+ capable and LCD function supplied by VLCD. Can be configured to work as a ADC1_IN12 pin

23. PA8: Same functions as PA1. Can be configured to work as a ADC1_IN15 pin.

24. PA9: Same functions as PA7. Can be configured to work as a ADC1_IN16, I2C1_SCL and COMP1_INM pin.

25. PC4: I/O pin, 5V tolerant. Analog switch function supplied by VDDA and LCD function supplied by VLCD. Can be configured as a COMP1_INM and ADC1_IN13 pin.

26. PC5: Same as PC4. Can be configured as COMP1_INP, ADC1_IN14, WKUP5.

27. PB2: I/O pin, 5V tolerant. Analog switch function supplied by VDDA. Can be configured as a COMP1_INP and RTC_OUT pin.

28. PB10: I/O pin, 5V tolerant. LCD function supplied by VLCD. Fm+ capable. QUADSPI_CLK.

29. PB11: Same as PB10.

30. VDD (Pin 30, 68 and 45): Supply pins. The VDD pin is the digital power supply voltage for the internal digital circuitry. This pin is typically connected to an external power supply, such as a battery or voltage regulators. The recommended operating range is between 1.71V and 3.6V. To ensure stable VDD operation, it is essential to decouple and filter the power supply. This can be achieved by, connecting a 100 nF ceramic capacitor between VDD and GND, adding a 10 uF chemical capacitor in parallel for further filtering and tying all VDD pins together and connecting them to the power supply plane. There are multiple VDD pins to maintain the signal integrity of signals reaching modules in the Chip. For example, one VDD would be connected to the CPU/Cache and other VDD pins for other modules.

31. RF1: RF and I/O pin. The RF1 pin is used for transmitting and receiving radio frequencies within the 2.4-2.5 GHz bandwidth, which is the Bluetooth frequency range. STM32 series chips are typically compatible with Bluetooth and include an onboard radio module for this purpose. When configuring this pin, ensure to add multiple low-pass filters before connecting the antenna to block unwanted frequencies, as the radio module is highly sensitive.

32. VSSRF: Supply pin. This pin serves as the return path for VDDRF and must be connected to ground to ensure proper operation of the RF module.

33. VDDRF: Supply pin. This pin is a dedicated power supply input for the RF circuitry. Its primary purpose is to provide a separate and independent power supply for the RF transceiver. This pin must be connected to the same power supply as the VDD. 1.71V-3.6V.

34. OSC_OUT: RF pin. 32 MHz main oscillator output (feedback pin).

35. OSC_IN: RF pin. 32 MHz main oscillator input (excitation pin).

36. AT0: RF pin. Reserved production test pin. According to ChatGPT this pin is used for antenna selection and switching. It allows the microcontroller to switch between different antennas or antenna configurations.

37. AT1: RF pin. Reserved production test pin. According to ChatGPT this pin is used for antenna tuning and matching. It helps to adjust the impedance of the antenna to optimize RF performance.

38. PB0: I/O pin, 3.6V tolerant. RF_TX_MOD_EXT_PA.

39. PB1: I/O pin, 3.6V tolerant. LPUART1_RTS_DE.

40. PE4: I/O pin, 5V tolerant.

41. VFBSMPS: Supply pin. SMPS Feedback voltage. 1.4V to 3.6V. Should be connected to the ground. It is not possible to use this SMPS output to supply any external circuitry, as its current and voltage capability are impacted by internal device states.

42. VSSSMPS: Supply pin. Ground for SMPS step-down converter.

43. VLXSMPS: Supply pin. This pin is the switched SMPS step-down converter output. Should be connected to ground, unless we need to analyse it.

44. VDDSMPS: Supply pin. This pin is the external power supply for the SMPS step-down convertor. It must be connected to the same supply as the VDD pin.

46. PB12: I/O pin, 5V tolerant. LCD function supplied by VLCD. Configurable as I2C3_SMBA (System Management Bus Alert). This pin configuration is used for devices which want to use an interrupt line instead of acting as a master.

47. PB13: I/O pin, 5V tolerant. LCD functioned supplied by VLCD. Fm+ capable. I2C3_SCL.

48. PB14: Same as PB13. I2C3_SDA.

49. PB15: Same as PB 12. SPI2_MOS.

50. PC6: Same as PB 12.

51. PA10: Same as PB 13. I2C1_SDA.

52. PA11: I/O pin, 5V tolerant. USB function supplied by VDDUSB. USB_DB, used for the negative terminal of the USB communication interface, specifically the 'negative' part of the differential data lines.

53. PA12: Same as PA11. USB_DP, used for the positive terminal of the USB communication interface, specifically the 'positive' part of the differential data lines.

54. PA13 (JTMS_SWDIO): Same as PA 11. Can be configured as JTMS-SWDIO, which is a JTAG/SWD (Serial wire Debug) interface. This pin is one of the pins used for programming the chip.

55. VDDUSB: Supply pin, 3.0V-3.6V. This is an external independent power supply for the USB transceiver in the STM32, being a dedicated voltage supply for the USB peripheral. When USB is not used, it must be connected to VDD and decoupled with a 100nF ceramic capacitor.

56. PA14 (JTCK_SWCLK): I/O pin, 5V tolerant. LCD function supplied by VLCD. JTCK_SWCLK, is the Clock pin for SWD programming.

57. PA15 (JTDI): Same as PA14. JTDI, this is used specifically for debugging and programming purposed and part of the JTAG (Joint Test Action Group) interface, enabling single-step execution of code for debugging. This pin is additionally used for facilitating firmware updates and flash programming.

58. PC10: I/O pin, 5V tolerant. LCD function supplied by VLCD.

59. PC11: Same as PC10.

60. PC12: Same as PC10.

61. PD0: I/O pin, 5V tolerant.

62. PD1: Same as PD0.

63. PB3 (JTDO): I/O pin, 5V tolerant. Analog switch function supplied by VDDA and LCD function supplied by VLCD. JTDO serves as the output of the JTAG TAP (Test Access Port) when the device is in debug mode. JTDO pin output TCK (Test Clock) signal, which is used to synchronise the JTAG TAP with the external debugger, allowing the debugger access to the microcontroller’s modules.

64. PB4 (NJTRST): I/O pin, 5V tolerant. Analog switch function supplied by VDDA and LCD function supplied by VLCD. Fm+ capable. NJRST is a separate reset signal for the SWD interface and used to reset the SWD logic and TAP controller. This pin is sometimes connected to ground when using SWD, preventing accidental resets. SPI1_MISO.

65. PB5: I/O pin, 5V tolerant. LCD function supplied by VLCD. SPI1_MOSI.

66. PB6: I/O pin, 5V tolerant. Analog switch function supplied by VDDA and LCD function supplied by VLCD. Fm+ capable. COMP2_INP, USART1_TX.

67. PB7: Same as PB6. COMP2_INM, USART1_RX.

69. EPAD: A metal pad located on the underside of the STM32, used primarily for thermal management, mechanical stability and electrical grounding. The EPAD has a large surface contact area with the PCB, making it easier to dissipate the heat. By grounding the chip at this point, the electrical noise is reduced and the overall grounding improved.

Discussion (GPIO Pin Modes):

The GPIO pins on the STM32 can operate in five different modes: Input Mode, Output Mode, Alternate Function Mode, Analog Mode, and Pull-up/Pull-down configuration. Each pin is identified by its GPIO function, such as PA2, which refers to bit 2 of Port A, and PB3, which refers to bit 3 of Port B.

Input Mode:

The STM32 microcontroller interprets the level as HIGH or LOW depending on the voltage thresholds. The actual voltage levels depend on the supply voltage VDD and are typically expressed as a percentage of VDD. Assuming the VDD is 3.3V, the maximum voltage that will be considered LOW is usually around 0.3 * VDD which is around 0.99V and the minimum voltage that will be considered HIGH is 0.7 * VDD which will be around 2.31V.

Output Mode:

When in LOW Output mode the pin usually outputs a voltage close to 0V and when in HIGH Output mode, the pin outputs a voltage that is close to the VDD.

FET Transistors in GPIO Operation:

FET transistors, specifically MOSFETS, Metal-Oxide-Semiconductor Field-Effect Transistors play a critical role in controlling the GPIO pins in STM32 MCUs. Each GPIO pin is basically controlled by two MOSFETs – one for driving the pin high (PMOS) and one for driving it low (NMOS).

• NMOS Transistor (Low Output) (NMOS transistor switches off when a current is present and on when none is present): When the MCU sets the GPIO pin to a LOW state, the NMOS transistor is turned on (allowing current to flow to ground), whilst the PMOS is turned off, essentially pulling the pin to ground.
• PMOS Transistor (HIGH Output) (PMOS transistor switches on when a current is present and off when none is present): The MCU sets the GPIO pin to a HIGH state by turning on the PMOS transistor (allowing the current to flow from the VDD) and turning the NMOS transistor off, pulling the pin up to the supply voltage.
• Input Mode: In Input Mode, both transistors are typically off to allow the external signal to control the pin voltage, The pin state is read by a voltage comparator inside the STM32, which uses the previously mentioned thresholds VDD to determine whether the input is HIGH or LOW.

Basic PCB design:

Power supply decoupling:

All power supply and ground pins must be properly connected to the power supplies. These connections, including pads, tracks and vias should have as low impedance as possible. This is typically achieved with thick track widths and, preferably, the use of dedicated power supply planes in multilayer PCBs. In addition, each power supply pair should be decoupled with filtering Ceramic capacitors (100 nF) and one single Tantalum or Ceramic capacitor (min. 4.7 µF typ. 10 µF) connected in parallel. These capacitors need to be placed as close as possible to, or below, the appropriate pins on the underside of the PCB. Typical values are 10 nF to 100 nF, but exact values depend on the application needs. Figure 22 shows the typical layout of such a VDD/VSS pair.

Pull up/Pull down:

To increase EMC performance, unused clocks, counters or I/Os, should not be left free, e.g. I/Os should be set to “0”or “1” (pull up or pull-down to the unused I/O pins) and unused features should be frozen or disabled.

To reduce leakage, it is advisable to configure the I/O as an analog input or to push-pull and to set it to “0”.

Differential Data Lines (USB C D+/D- pins |PA11/PA12):

When using differential data lines, the signals are typically transmitted over a pair of interwoven wires. These wires are tightly coupled, creating a controlled impedance and containing the electric and magnetic fields between them. This results in a "true" differential pair, where any common-mode noise is equally coupled into both lines, subjecting them to approximately the same amount of interference.

In this configuration, the signals reference each other rather than relying on a ground reference, effectively ignoring ground offsets. This design enhances noise immunity and signal integrity.

On PCB trace we are working on a 2-axis system rather than 3-axis system, making it much harder to create a perfect differential pair. There are many factors to consider here, but first the basics should be understood.

The diagram represents our differential pair. The grey arrow indicates minor coupling or energy in the circuit, commonly referred to as "crosstalk." This crosstalk accounts for approximately 10-20% of the total coupling. Most of the coupling, around 80-90%, occurs between the reference plane (typically the ground) and the individual transmission lines. In this setup, the lines cannot effectively use each other as a reference, so the ground (GND) is predominantly used as the reference point.

In our 2-axis system, we must consider that the impedance and coupling vary depending on the width of the individual transmission lines and the distance between them. The closer these traces are to each other, the greater the coupling, which decreases the impedance between the lines. Additionally, if the trace is wider, the capacitance between the trace and the reference plane increases, thereby decreasing the impedance of the trace itself.

To account for the impedance characteristics of each individual trace, we use what is called the differential impedance, defined as 2*(impedance of the individual wire – impedance due to coupling), this being the total impedance of the two traces. Therefore, as the distance between the two lines decreases, the differential impedance decreases as well. Similarly, if the width of the trace increases, the differential impedance also decreases.

In PCB design, it's crucial to ensure that the trace lengths of a differential pair are as close as possible to minimize skew, a practice known as intra-pair matching. Skew occurs when there is a time difference in the arrival of signals on the two traces, which can degrade signal integrity. Ideally, the maximum allowable skew should be limited to around 5 picoseconds.

The diagram illustrates how the second trace is routed to match the length of the first trace, thereby reducing skew and ensuring that the signals remain synchronized as they travel through the differential pair.

In situations where a communication device has multiple differential pairs, it's important to keep these pairs in sync, which requires their trace lengths to be similar. However, the skew tolerance between different differential pairs can be more lenient compared to within a single pair. In these cases, the allowable skew might range from 10 picoseconds to hundreds or even thousands of picoseconds, depending on the specific application and timing requirements. The diagram shows inter-pair tracing. In certain dips the first trace travels a shorter distance than the second, and in other dips the first trace tavels a longer distance than the second trace, reducing the skew.

Another important aspect to consider when designing traces for differential pairs is termination. When transmitting high-speed digital data—especially with short rise and fall times over long transmission lines—there could possibly be impedance mismatches between the output driver (Zsource), the transmission line (ZTL), and the load (ZL). Any mismatches in these impedances can lead to reflections, which, if significant, may result in overshoots and undershoots. These effects can cause signal integrity issues, such as exceeding maximum voltage ratings or violating logic margins. Moreover, impedance mismatches can negatively impact the system's electromagnetic interference (EMI) performance, leading to increased ringing, higher frequency content, and overall reduced signal quality. Termination aims to reduce the magnitude of these reflections by matching the impedances.

Many types of termination are possible, including series termination (a resistor placed in series with the driver output) and parallel termination (a resistor placed in parallel at the load and connected to a reference voltage). To evaluate the potential reflections in a given trace connection, we use the reflection coefficient. The reflection coefficient (Γ) is calculated as the difference between for example the load impedance and the trace impedance (typically 50 ohms), divided by their sum:

Ideally we want ZS = ZTL = ZL, giving a reflection coefficient of 0, and thereby giving perfect power delivery. If ZL > Z0 we get positive reflections (reflection adds to incident) and thus an overshoot and if ZL < Z0 we get negative reflections (reflection subtracts from incident) and thus an undershoot.

Power Pin Schematics:

VDDSMPS:

• 2 ceramic decoupling capacitors, each 4.7uf and 100nf respectively.

VDD:

• 3 100nf ceramic capacitors for decoupling of each VDD pin and an additional 4.7uF ceramic/tantalum capacitor.
• TVS Diode to attenuate voltage spikes.

VDDA:

• 100nf ceramic capacitor for decoupling and an additional 1uF ceramic/tantalum capacitor.
• TVS Diode to attenuate voltage spikes.

VREF:

• 100nf and 1uF ceramic capacitor presumably for filtering?

VDDUSB:

• 100nf ceramic capacitor for decoupling
• TVS Diode to attenuate voltage spikes.

VDDRF:

• `100pf and 100nF ceramic capacitors for decoupling.

VLXSMPS/VFBSMPS:

• 4.7uF ceramic capacitor and 10uH inductor for filtering.