FPGA watch (with button function) on Zybo Z7

Notice

This project was designed based on "Matbi Watch" of matbi.

Address : https://www.hackster.io/matbi/matbi-watch-on-zybo-z7-using-verilog-hdl-135771

I'm a subscriber to his youtube.

Matbi Watch Button Plus 1 Top (Core)

I re-designed the "Matbi Watch Top" module to make it work. And I added a variable on "Matbi sec gen" module.

Matbi Watch Button Plus 1 Top can not only create seconds, minutes, and hours values every cycle when the activation signal is high, but also increment the minutes and hours when a button is pressed.

1) "Matbi one sec gen btn gen" is to count cycle and generate one sec tick. In addition to, it is to count 3/4 of cycle and generate btn tick.

(I designed this module, Pressing Button function is properly activated on 100MHz. This is because at smaller frequencies, the button press feature is not necessary.)

2) Using the signal of "one sec tick", It can be generate sec, min and hour values. And It can be added min or hour by pressing the button.

If you press BTN[0], one minute is added. And If you press BTN[1], one hour minute is added.

Counting cycle and button actions work together as a flow.

Because pressing Button can only be detected between 1 second increments.

Micro Architecture:

port list:

IP TOP

I did add a variable "btn[3:0]" as input. And I fixed the instance part. The rest is the same as "lab3_matbi.v" of matbi.

I connected controller (myip_v1_0.v) to control matbi_watch_top and check time results. I used I/F AXI4-Lite and basic signals such as clock, reset, enable.

"Enable signal" is input, I have a plan to connect switch on zybo Z7.

The matbi watch only runs when the switch is turned on.

HW System

1) Call IP top and PS

2) Change Frequency 100MHz, it is possible to synthesis design on Zybo Z7-20. And Tunr on UART1.

3) Click the "auto connection".

4) Create HDL wrapper. And generate Bitstream.

SWI

Register table is here. You can also easily program SW code.

Run - input freq value: 100, 000, 000

Summary

I learned a lot about testbench, multiple problem of generate bitstream using Vivado tool, etc while I was working on this project. And it was an opportunity to improve my personal skills.