AMD Spartan™ 7 FPGA Stamp Design

Introduction

Small FPGAs in the AMD range, such as the AMD Spartan™ 7 and AMD Artix™ 7, are ideal for many applications as they provide determinism, low latency, and very flexible I/O.

In this project, we are going to create a small module containing an AMD Spartan 7 FPGA, along with its supporting components to create a stamp. This stamp will be a simple, small PCB that can be easily included in other projects, eliminating the need to design from scratch every time.

The goal is not only to make it as small and low-cost of a stamp as possible, but also to find a use for several Spartan 7 FPGA devices that I have left over from another project.

Due to the nature of this project, as we are designing a physical element, we will not be able to test the final design immediately.

As such, this project will address the development of the requirements, architecture, component selection, and the schematic design.

Once that is completed, I will be sending the board out for layout and manufacturing.

There will be a follow-on project with the testing and bring up of the Spartan 7 FPGA stamp.

The schematics and layout will be made available in the source format for those who want them.

Requirements

All projects should begin with a set of requirements that define the functional and non-functional behavior of the project. These requirements will also provide the interfacing requirements.

• REQ1 - The stamp shall include a AMD Spartan 7 XC7S6 FPGA in a CSGA225 package.
• REQ2 - The stamp should be designed to accommodate larger values in the AMD Spartan 7 FPGA range, including the XC7S15 and XC7S25.
• REQ3 - The stamp shall provide non-volatile memory to store the FPGA configuration stream.
• REQ4 - The stamp shall be implemented in a square format
• REQ5 - The stamp shall provide 20 I/O on each edge of the square
• REQ6 - Where possible I/O supporting differential pairs should be used
• REQ7 - The stamp shall provide JTAG via its I/O pins
• REQ8 - The stamp should provide programming over USB
• REQ9 - Configuration of the FPGA shall be selectable between NVRAM and JTAG
• REQ10 -The stamp shall provide a 25 MHz Oscillator
• REQ11 - The stamp shall be supplied by 5V
• REQ12 - The stamp shall generate all of the necessary core and IO voltages.
• REQ13 - Multiple 5V inputs shall be supplied - at least one per side
• REQ14 - Multiple grounds shall be supplied - at least one per side
• REQ15 - Connections shall be spaced to allows 0.1 inch pitch headers to be fitted
• REQ16 - The stamp shall provide at least one LED accessible by the user

Architecture

The next step in the process is to create an architecture that reflects the requirements. Although this is fairly simple, it is still worth doing.

The power element will take in 5V from the board and generate the core, auxiliary, and I/O voltages for the FPGA. Configuration data will be stored within the NVRAM, while the USB JTAG will provide programming capabilities for the FPGA and the NVRAM memory.

It is envisaged that on the JTAG output between the USB JTAG and the FPGA, there will also be headers connected to enable direct JTAG access using a Digilent HS3 or Smart Link programmer.

The oscillator will be a standard 100MHz and will enable a range of frequencies to be created using internal PLLs.

Compliance Matrix

In a professional engineering project, a compliance matrix is the method by which we demonstrate our solution's compliance with the requirements.

The compliance matrix demonstrates that we are compliant, apart from one requirement, which is partially compliant. The partial compliance arises because we will provide the USB JTAG programming device on the stamp; however, the actual USB connector will not be implemented on the stamp. This allows the user of the stamp to position the USB connector where it is best for them.

Background Reading

Before we jump off and start creating schematics we need to do some background reading to ensure we are designing the system in the correct manner to help me design this the I read the following

• AMD 7 Series FPGA PCB Design Guide
• AMD 7 Series FPGA SelectIO Resources
• AMD 7 Series FPGA Packaging and Pinout
• AMD 7 Series FPGA Clocking Resources
• AMD 7 Series FPGA Configuration

Design

Before we jump into the schematic process, we need to undertake some design and, some analysis to ensure our system will work as expected.

The first step is to ensure we have an accurate power estimation, which will inform the sizing of the power design.

The main power draw will be from the FPGA. As such, we need to create an accurate power estimation.

To do this, we can use one of the AMD power estimation spreadsheets.

This tool allows us to define the resource utilization, clock rates, and toggle rates to determine an accurate power estimation for the device.

As the XC7S6 is the lowest capacity device available, the devices will typically have high utilization.

As such, the power estimation will assume that all of the resources of the FPGA are used.

This gives me a total on-chip power estimation of 0.351 W.

Power Breakdown and graphs

Logic Utilization

We also need to select other components so we can determine the power requirements for them. The major components are

• FT232H - USB to JTAG chip
• 93LC56BT - JTAG PROM used with FT232H
• IS25LP256D - FPGA PROM holds the configuration
• KC2520Z100.000C15XXK - 100 MHz oscillator

The baseline FPGA requires 4.3 Mbits of configuration memory, and we also want to support the XC7S25 device, which requires 9.9 Mbits of configuration data. As such, we have selected a 256 Mb QSPI memory. This will provide developers with the ability to implement multiboot and fallback solutions.

I selected the FT232H because it is one of the devices supported by the AMD Vivado ™ Design Suite for programming over USB to implement USB JTAG functionality.

The next step, with the components identified, is to create an overall system power budget to ensure the power solution is correctly scoped.

The power device selected is the RICHTEK RT7273GQW, a three-output switching regulator capable of 3A outputs, which will be more than sufficient.

The benefit of the three-channel design is that it is very compact and enables a smaller solution than would be possible with three discrete power supplies.

From the datasheet of the RT7273, we need to determine the maximum and minimum power efficiency for the predicted efficiency and the worst-case load currents.

We must take into account the efficiency of the selected power switching converters.

With the components selected, and the power estimation determined we can now start the creation of the schematics for the module.

With the components selected and the power estimation determined, we can now start creating the schematics for the module.

Schematics

To create the schematics, I have used Altium Designer, a tool I have owned for some time but have not personally used recently. The schematics are organized in a hierarchical design, allowing for reuse across several projects if needed.

The elements of the design are:

• Power: This module creates the 1v0, 1v8, and 3v3 power from the input voltage.
• NVRAM: This module contains the non-volatile configuration memory.
• FPGA: This contains the AMD Spartan 7 XC7S6 device and breaks out the I/O.
• JTAG: This module contains the FTDI FT4232 device, which provides JTAG access to the FPGA and programs the NVRAM.

In keeping with most of my designs, I like to keep the top level as simple as possible. Schematics are attached to the project at the bottom.

The power design element is outlined below—this generates the 1v0, 1v8, and 3v3 voltages required. I have included test points on each of the output and input rails, as well as several test points on the ground.

My plan for the layout, is to provide two interface methods. The first will be castellations which can be soldered to surface-mount the board.

The second, and what I will most likely use for bring-up, is to make a 0.1-inch header mating hole for each castellation.

Consequently, for power and ground, I have added five pins for each. We can modify the footprint to the desired shape once we get to the layout stage.

The NVRAM setup is quite straightforward, as illustrated below. I have added pull-up resistors and, series termination resistors, in case they are needed.

The most complex element of the design is the FPGA page. On this page, we handle the configuration settings, the I/O allocation, and, the power connections.

The first step is to allocate the external I/O of the stamp in accordance with the requirements. I plan to make the JTAG pins available, along with VIN and Ground. To enhance the flexibility of the design, I will allow BANK 34 to use a selectable I/O voltage, which can be powered by whatever the stamp is mounted on.

The total user IO will be 77 Pins.

To simplify the FPGA page as much as possible, I will use a hierarchical structure to manage the unused I/O along with the power and ground connections.

To program the design, we need to implement a JTAG interface. My plan involves using a USB and an FTDI device programmed via AMD Vivado. To maintain flexibility in the stamp, I will not implement the USB connector directly on the stamp.

Instead, I will break out the DP and DM signals to the edge castellation's. I also plan to make the JTAG signals available on the edge castellation's. The reason for this is to enable the creation of JTAG chains if desired on the system that uses the S7 Stamp.

Next Steps

The project has completed layout and is out for manufacture. Some shots from the progress of the design can be seen below.

There will be another project later in the summer, once I have the stamp in hand. That project will hopefully focus on the bring-up of the design.

Sponsored by AMD