Creating a Zynq or FPGA-Based, Image Processing Platform

Overview

This project will demonstrate how to create a simple image processing platform based on the Xilinx Zynq. This project will then be used as a base for later developments which focus upon High-Level Synthesis based development which allows the use of the industry standard OpenCV library.

To create this example I am using a Zybo Z7 as it provides both HDMI input and output, along with a CSI-2 interface for a MIPI camera which we can use also for future developments.

In addition to the Zybo-Z7 we will be using:

• HDMI Camera e.g. the Apeman 1080P action camera

• Associated cables for HDMI In and Out ports

• HDMI Display

To create the application we will be using the following development tools & libraries:

• Vivado 2017.4

• Xilinx SDK 2017.4

• Digilent Vivado Library

To create this example we need to perform the following preparatory steps:

• Download and extract the Digilent Vivado Library to your computer

• Install the Digilent Board definitions, if you are unsure how to do this click here

• Create a new Vivado project targeting the Zybo-Z7

• Create a new block diagram within Vivado

Components

Inside the Vivado block diagram we need to add the following IP:

Zynq Processing System - This will provide the configuration and control of the image processing system, while its DDR is used also as a frame buffer ensure the following configuration

• PL Clock 0 = 200 MHz

• PL Clock 1 = 100 MHz

• HP 0 Slave enabled - this will be used to transfer images to and from the PS DDR

• GP 0 Master enabled - this is used to configure the image processing chain

DVI2RGB - This converts the HDMI video stream into a 24 bit RGB bus with appropriate vertical and horizontal syncs.

AXI GPIO - A single output used to assert the hot plug detect on the HDMI Source, failure to assert this may mean there is not video received.

Video Timing Controller - Configured for detection, this will detect the mode of the video received from the HDMI source.

Video In to AXIS - This converts the parallel video and syncs into a AXI Stream. Along with the image data on TDATA, the start of frame is identified by the TUser signal while the end of line is identified by the TLast signal.

Configure this to have independent clocks so that the pixel clock and AXI stream clocks are different.

AXIS Subset Converter - This component remaps the format of the 24 bit video output into the correct RGB format. Two of these are used before and after the VDMA.

Video Direct Memory - The write channel moves the AXI Stream video into a AXI Memory mapped form for storage in the PS DDR memory. While the read channel accesses the PS DDR and converts the AXI Memory Mapped format into a AXI stream for output. Ensure both directions are enabled.

Video Timing Controller - This is configured as a timing source, this is configured with the timing required dependent upon the input video timing. This is used by the AXIS to Video Output to generate the output parallel video and syncs

RGB2DVI - This converts the output parallel video and vertical and horizontal syncs to HDMI

To support the configuration of the output clocks dynamically the Dynamic Clock Generator is used from the Digilent Vivado Library. This allows the pixel clock frequency to be changed over using AXI lite dependent upon the received video format.

Vivado Project

Putting all of this together enables the creation of a Vivado project as shown below.

The Vivado project can then be built and exported to Xilinx SDK to enable us to create the application SW.

Within Xilinx SDK we need to write our software application to do the following:

• Assert the GPIO connected to the HDMI IN Hot Plug Detect - after asserting this signal the processor waits 5 seconds to ensure the HDMI Source generates video.

• Configure the Video Timing Controller (Detector) to report the incoming video mode.

• Configure the Video Timing Controller (Generator) to generate timing as per the detect video mode.

• Configure the dynamic clock

• Configure the VDMA to have read and write data from the PS DDR

Running the application SW should then enable you see the an image on your chosen HDMI source.

Demo

This provides us an idea platform which we can use in future to demonstrate our HLS image processing based applications.

If you want to know more about using the Zynq check out: www.microzedchronicles.com