One of the great things about AMD FPGAs is they include a small ADC which enables internal voltages and temperatures to be monitored. This can be exceptionally useful during board bring up and even for security and functional safety.
Another great aspect is these ADCs are able to receive external signals. This reduces BOM cost and allows us to offer a tightly integrated solution.
However, sometimes we want to be able to generate an analogue signal from the FPGA. In this case we have two options
- Use an external DAC - This comes with board space and costs but for high frequency solutions is often the best approach
- Use an over sampling digital approach within the FPGA itself and filter the signal externally with a low pass filter.
When it comes to looking at the over sampling approaches we can use either a Pulse Width Modulation scheme or a delta sigma approach. These output a signal the average of which is the analogue signal which is being recreated.
To recover the signal we use an low pass filter external to the FPGA to recover the signal.
Pulse Width ModulationThe simplest of the two schemes is to use a PWM signal to generate the analogue signal.
A PWM signal has two key elements
- Period - The repetition period of the signal
- Duty Cycle - How much of period the signal is high
For a PWM signal we can vary the duty cycle to generate an analogue signal for recovery by low pass filter.
To create a sine wave using the PWM we need to vary the PWM duty cycle in accordance with Sine wave amplitude.
The best way to do this is to plot the sine wave and segment it into 12 separate segments each which covers 30 degrees and then measuring the amplitude.
From this plot we can use duty cycles of 0%, 7%, 25%, 50%, 75%, 93% and 100% to recreate the sine wave.
We can therefore generate a sine wave using a PWM which is output in the following sequence
75%, 93%, 100%, 93%, 75%, 50%, 25%, 7%, 0%, 7%, 25%, 50%
We can do this simply with a look up table and a PWM counter very simply in RTL.
If we want to generate a sine wave at 1KHz, generate the PWM output waveform at least 12 times faster than that if we have segmented the waveform into 12 elements.
This means our PWM frequency needs to be 12000 Hz or have a period of 83.333 Micro Seconds.
With a 100 MHz clock (period of 10 ns), this means we need a counter which can count to 8333, this requires a 14 bit counter in our RTL.
A simple look up table was created for each of the PWM widths required.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pwm_sine is port(
i_clk : in std_logic;
o_pwm : out std_logic
);
end entity;
architecture rtl of pwm_sine is
constant upper_width : integer := 14;
constant max_count : integer := 8333;
type t_sine_array is array (0 to 11) of unsigned(upper_width-1 downto 0);
constant analog_wave : t_sine_array := (
to_unsigned(6250 ,upper_width),
to_unsigned(7750 ,upper_width),
to_unsigned(8333 ,upper_width),
to_unsigned(7750 ,upper_width),
to_unsigned(6250 ,upper_width),
to_unsigned(4166 ,upper_width),
to_unsigned(2083 ,upper_width),
to_unsigned(583 ,upper_width),
to_unsigned(0 ,upper_width),
to_unsigned(583 ,upper_width),
to_unsigned(2083 ,upper_width),
to_unsigned(4166 ,upper_width));
signal s_counter : unsigned(upper_width-1 downto 0):=(others=>'0');
signal s_wave_pos : unsigned(3 downto 0):=(others=>'0');
begin
process(i_clk)
begin
if rising_edge(i_clk) then
if s_counter = max_count - 1 then
s_counter <= (others=>'0');
if s_wave_pos = 11 then
s_wave_pos <= (others => '0');
else
s_wave_pos <= s_wave_pos + 1;
end if;
else
s_counter <= s_counter + 1;
end if;
end if;
end process;
process(i_clk)
begin
if rising_edge(i_clk) then
o_pwm <= '1' when s_counter < analog_wave(to_integer(s_wave_pos)) else '0';
end if;
end process;
end architecture;The delta-sigma is a one-bit DAC that requires only a simple RC filter on the output to recover the signal. To achieve this, the sampling rate of the signal is much higher than the input signal. The delta-sigma works by ensuring the average output level represents the average input level, generating a pulse proportional modulation (PPM) output signal.
A first-order delta-sigma converter has the following design:
We can implement this very simply in VHDL using the fixed-point package. All we need to do is implement an accumulator, strip off the MSB as the output, and then determine what the feedback value is to be fed back into the accumulator along with the next input signal.
For this example, I am going to create a 16-bit DAC and an associated test bench. The test bench will use the output from a Python script to determine the waveform we wish to sample.
First, let's look at the VHDL 2008 RTL code. I have used a standard logic vector input for the sample data along with a valid signal. This could be easily connected to an AXIS peripheral further up in the processing chain; just tie Tready high.
The use of standard logic on the ports enables me not to worry about type conversions in the architectural VHDL for larger projects. The value passed across in the port is treated as a signed 16-bit value internally, with a value between +/- 0.99999.
Inside the RTL, I have created two signals, both 20 bits long, and used the fixed-point package signed type. One of these acts as the accumulator and the other as the feedback signal from the one-bit DAC looking at the output. As the input will be between +/- 0.99999, I have leveraged the fractional element of the signal definition in the fixed-point package.
signal s_accumulator : sfixed(3 downto -16) := (others =>'0');
signal s_feedback : sfixed(3 downto -16) := (others =>'0');The process itself is simple. If the sample valid input is high, the accumulator adds in the sample along with the feedback value. As the feedback value is meant to be subtracted, I inverted the values for the feedback to make it just an addition.
As we are using the fixed-point types, I needed to ensure the accumulator was sized correctly and used the resize option. This is because the size of the output needs to match the size of one of the inputs. I set the overflow style to wrap around should the accumulator saturate. To do this, I needed to add in the fixed-point type package.
v_accum_temp := resize (arg => (s_accumulator + to_sfixed(
i_sample_data,-1,-16)- s_feedback),
size_res => s_accumulator,
overflow_style => fixed_wrap);The output is generated as a 0 when the value of the accumulator is less than 0 and 1 in other cases. The final determination is the feedback signal, which is -1 when the output is high and 1 when the output is low to account for the difference subtraction.
s_feedback <= to_sfixed(-1,3,-16) when o_dac_op = '1' else to_sfixed( 1,3,-16);The FPGA design will include both the 1st Order Delta Sigma and the PWM design. We will route this out over the first Pmod output using Pin 1 (delta sigma) and pin 2 (PWM).
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.p_wave_Package.all;
entity delta_sigma_dac_top is port(
i_clk : in std_logic;
o_pwm : out std_logic;
o_dac : out std_logic);
end entity;
architecture bench of delta_sigma_dac_top is
constant c_sequence_len : integer := 1000;
constant c_wave_len : integer := 100;
signal s_sample_val : std_logic;
signal s_sample_data : std_logic_vector(15 downto 0);
signal s_dac_op : std_logic;
signal s_count : integer := 0;
signal s_sample_count : integer := 0;
begin
delta_sigma_dac_inst : entity work.delta_sigma_dac
port map (
i_clk => i_clk,
i_sample_val => s_sample_val,
i_sample_data => s_sample_data,
o_dac_op => s_dac_op
);
o_dac <= s_dac_op;
stim: process(i_clk)
begin
if rising_edge(i_clk) then
s_sample_data <= analog_wave(s_sample_count);
s_sample_val <= '1';
if s_count = ( c_sequence_len - 1 ) then
if s_sample_count = ( c_wave_len - 1) then
s_sample_count <= 0;
else
s_sample_count <= s_sample_count +1;
end if;
s_count <= 0;
else
s_count <= s_count + 1;
end if;
end if;
end process;
pwm_inst : entity work.pwm_sine
port map(
i_clk => i_clk,
o_pwm => o_pwm
);
end architecture;The stimulus package is
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
package p_wave_Package is
type t_sine_array is array (0 to 99) of std_logic_vector(15 downto 0);
-- put python results below
constant analog_wave : t_sine_array := (
"0000000000000000",
"0000100000001001",
"0001000000001010",
"0001011111111011",
"0001111111010100",
"0010011110001101",
"0010111100011110",
"0011011001111111",
"0011110110101001",
"0100010010010101",
"0100101100111011",
"0101000110010110",
"0101011110011110",
"0101110101001110",
"0110001010011111",
"0110011110001101",
"0110110000010010",
"0111000000101001",
"0111001111010000",
"0111011100000001",
"0111100110111011",
"0111101111111001",
"0111110110111010",
"0111111011111100",
"0111111110111110",
"0111111111111111",
"0111111110111110",
"0111111011111100",
"0111110110111010",
"0111101111111001",
"0111100110111011",
"0111011100000001",
"0111001111010000",
"0111000000101001",
"0110110000010010",
"0110011110001101",
"0110001010011111",
"0101110101001110",
"0101011110011110",
"0101000110010110",
"0100101100111011",
"0100010010010101",
"0011110110101001",
"0011011001111111",
"0010111100011110",
"0010011110001101",
"0001111111010100",
"0001011111111011",
"0001000000001010",
"0000100000001001",
"0000000000000000",
"1111011111110111",
"1110111111110110",
"1110100000000101",
"1110000000101100",
"1101100001110011",
"1101000011100010",
"1100100110000001",
"1100001001010111",
"1011101101101011",
"1011010011000101",
"1010111001101010",
"1010100001100010",
"1010001010110010",
"1001110101100001",
"1001100001110011",
"1001001111101110",
"1000111111010111",
"1000110000110000",
"1000100011111111",
"1000011001000101",
"1000010000000111",
"1000001001000110",
"1000000100000100",
"1000000001000010",
"1000000000000001",
"1000000001000010",
"1000000100000100",
"1000001001000110",
"1000010000000111",
"1000011001000101",
"1000100011111111",
"1000110000110000",
"1000111111010111",
"1001001111101110",
"1001100001110011",
"1001110101100001",
"1010001010110010",
"1010100001100010",
"1010111001101010",
"1011010011000101",
"1011101101101011",
"1100001001010111",
"1100100110000001",
"1101000011100010",
"1101100001110011",
"1110000000101100",
"1110100000000101",
"1110111111110110",
"1111011111110111"
);
end p_wave_Package;While the python to generate the above package can be seen below
import math
import matplotlib.pyplot as plt
samples = 100
# Compute scaled sine values
sine_values = [math.sin(2 * math.pi * i / samples) for i in range(samples)]
scaled_values = [int(value * 32767) for value in sine_values] # Scale to signed 16-bit range
# Generate VHDL formatted sine values for std_logic_vector type
slv_values = ',\n '.join(f'"{value & 0xFFFF:016b}"' if value >= 0 else f'"{(value + 65536) & 0xFFFF:016b}"' for value in scaled_values)
# Print the values in VHDL array initialization format
vhdl_output = (
"constant SINE_WAVE : sine_array := (\n"
" " + slv_values + "\n"
");"
)
# Plot the sine wave
plt.figure(figsize=(10, 4))
plt.plot(sine_values, label='Normalized Sine Wave (-1 to 1)')
plt.plot([x / 32767 for x in scaled_values], label='Scaled Sine Wave (-32768 to 32767)', linestyle='--')
plt.title('Sine Wave (100 Samples over One Period)')
plt.xlabel('Sample Index')
plt.ylabel('Amplitude')
plt.grid(True)
plt.legend()
plt.show()
# Optionally, print VHDL output to console or output to a file
print(vhdl_output)The resource utilisation, of both implementations can be seen below
Of course, to recover the signal we need to use a filter to recover the analogue signal. The design of this filter and its component selection are of critical importance to the performance of the filter.
The easiest way to recover the signal is to use a low pass filter, for this we can use a simple RC filter.
To create the correct filter we need to decide on the cut of frequency of Fc. This is the frequency above which we wish to attenuate the signal.
The equation for a RC filter is as below
Fc = 1 / (2πRC)
I selected a Fc at 2 KHz and a capacitor value of 100 nF meaning we need a resistor of 820 Ohms.
With this RC combination we should have a filter which has a Fc of 1940 Hz, which is close enough to the 2KHz cut off.
To create the filters I used a PmodBB which provides the ability to connect connect the Pmod signals using bread board.
Using a simple first order RC filter worked well for the Delta Sigma output.
The FFT shows some Harmonics however, at significantly reduced amplitudes.
However for the PWM signal I found to reduce the harmonic I needed use a 2nd order RC filter. If I was designing this for a product I would probably use a multiple stage RC filter or active filter. This second filtering reduces the ripples on the sine wave but also decreases the amplitude and introduces a DC offset. For a real world application and not a project we might need to use some additional buffering or processing using an Op Amp etc.
The FFT of the sinewave shows some harmonics as would be expected.
When we compare the PWM output with the 1st order delta sigma we have a better solution using a delta sigma though we do
This project has shown how we can create a simple DAC output using two methods. Both methods us a simple RC filter to recreate the analogue signal and can be implemented simply within an FPGA. Of course we can implement this in any AMD FPGA or SoC device.
For better performance a 2nd order Delta Sigma DAC might be considered.
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