Published October 14, 2023 © GPL3+

A simple PELTIER temperature controller in VERILOG/Qspice

A simple PWM temperature controller is designed /simulated in VERILOG /Qspice with a NTC thermistor and a cooling PELTIER

IntermediateProtip2 hours247

A simple PELTIER temperature controller in VERILOG/Qspice

Things used in this project

Hardware components

Vishay NTCS0603 SMD thermistor 10 Kohms +/-1%

Vishay SI4136DY

Qorvo UF3C065030B3

Software apps and online services

Qspice

Story

A simple temperature controller coded in VERILOG in a Qspice simulation

A thermoelectric Peltier element cools down a heat source producing power peak in burst. The current within the Peltier is pulse width modulated (PWM) by the microcontroller, which reads the heat source temperature via a VISHAY NTC thermistor and compares the signal to a reference voltage. In the verilog controller coding, the signal of the NTC is converted by an ADC and compared to a sawtooth signal combining the digitized reference voltage and a counter. The switch on/off of the current on Peltier is performed by a Vishay n-channel MOSFET, whose gate voltage is triggered by the output of the controller.

We can see that the temperature of the object to cool (heat source) is swinging between 25 and 26°C, while 25°C is the reference temperature. The ambient temperature which surrounds the devices changes from 25°C to 30°C, which induces the PWM change from 0% to 100%.

The controller is also programmed to produce a 0 output if the NTC is in (partial) short circuit, which would normally induce a full working of the Peltier (for nothing).

update after the facts: the ADC is 8 bit . If we change to ADC 16 bit, the precision is much better.... and the execution time is shorter...... incredible.....all that you have to do is change the verilog code for the ADC module as follows.

module adc_x1 ( in, clk, out ) ;

input reg clk;

output reg [0:15] out;

integer result;

always @(posedge clk) begin

result = (in)/5*65535;

if (result > 55000) result = 0;

else if (result < 0) result = 0;

end

assign out = result;

endmodule

module counter ( clk, preset, nibble, out, matched ) ;

// You will probably want to flush out the nature of these port declarations:

input reg clk;

input reg preset;

input reg [0:15] nibble;

output reg [0:15] out;

output real matched;

// Implement the module here

always @(posedge clk or posedge preset)

begin

if(preset)

begin

out <=( nibble);

end

else

begin

out <= (out + 15'h01);

end

assign matched = out == nibble ? 1'b1 : 1'b0;

endmodule

There is a video on vimeo recapitulating the simulation result (pardon the background music) letsgetdigital_microcontroller_verilog2 on Vimeo

The simulation works as well with another MOSFET (Qorvo)UF3C065030B3 but the outpout OUT of the controller must be increased to 10V.

Code

***************************************
* SIMULATION OF MEASURING SYSTEM
* TAMB = AMBIENT TEMPERATURE
* SE = SEEBECK CONSTANT
***************************************
* modified for Qspice 02 oct 2023 from:
*SPICE model of thermoelectric elements including thermal effects
*February 2000Conference Record - IEEE Instrumentation and Measurement Technology Conference 2:1019 - 1023 vol.2
*DOI: 10.1109/IMTC.2000.848895
*SourceIEEE Xplore
*Conference: Instrumentation and Measurement Technology Conference, 2000. IMTC 2000. Proceedings of the 17th IEEEVolume: 2
*********************************
******** THERMAL CIRCUIT ********
*********************************
*** HEAT SINK ***
.subckt PELTIER4 H C I1 I2  Tambient OTC
.param SE=0.05292 Rp=1.806 Tinit=25
.IC V(1)={Tinit+273.15} V(2)={Tinit+273.15} V(3)={Tinit+273.15} V(4)={Tinit+273.15} V(OTC)={Tinit+273.15}
B2 3 0 V=V(Tambient)+273.15
RKRAD 4 3 0.34
CRAD 4 0 340
RSILH 4 1 0.143
*** THERMAL PELTIER MODEL ***
CH 1 0 2
BPE 0 1 I=-I(VPOS)*({RP}*I(VPOS)+{SE}*(V(1)-V(2)))
BPX 2 1 I=I(VPOS)*( {SE}*V(1)-{RP}/2*I(VPOS))
RKM 1 2 1.768
CC 2 0 2
*** THERMAL MASS ***
RSILC OTC 2 0.143
CCONINT OTC 0 304
RCONINT OTC 3 3.1
B3 H 0 V=V(4)-273.15
B4 C 0 V=V(OTC)-273.15
************************************
******** ELECTRICAL CIRCUIT ********
************************************
*** ELECTRICAL PELTIER MODEL ***
VPOS I1 13 0
RM 13 12 {Rp}
BALPHA 12 I2 V={SE}*(V(1)-V(2))
.ENDS
*****************************************

// Automatically generated .v file on Thu Oct 12 13:47:55 2023
//

module pwm_peltier_total_verilog3_microcontroller4_x12 ( in, vcc, in2, in3, clk, preset, out ) ;
// You will probably want to flush out the nature of these port declarations:
   input real in;
   input real vcc;
   input real in2;
   input real in3;
   input reg clk;
   input reg preset;
   output real out;

   // Implement the module here
reg [0:7] ntc;
reg [0:7] lim;
reg [0:7] out2;
reg [0:7] out3;
reg[0:7]nibble2;
real matched;

adc_x1 myadc(in,clk,ntc);
adc_x1 myadc2(in2,clk,nibble2);
counter mycounter(clk,preset,nibble2,out2,matched);
adc_x1 myadc3(in3,clk,lim);
limiter mylimiter(ntc,lim,out3);
comp_x4 mycomp(ntc,out2,out);

endmodule

module adc_x1 ( in, clk, out ) ;
// You will probably want to flush out the nature of these port declarations:
   input real in;
   input reg clk;
   output reg [0:7] out;

   // Implement the module here

integer result;

always @(posedge clk) begin
    result = (in)/5*255;
    if (result > 200) result = 0;
    else if (result < 0) result = 0;
end

assign out = result;

endmodule

module counter ( clk, preset, nibble, out, matched ) ;
// You will probably want to flush out the nature of these port declarations:
   input reg clk;
   input reg preset;
   input reg [0:7] nibble;
   output reg [0:7] out;
   output real matched;


   // Implement the module here
  always @(posedge clk or posedge preset)
   begin
      if(preset)
         begin

            out <=( nibble);

         end
      else
         begin
            out <= (out +  8'h01);


         end
   end

   assign matched = out == nibble ? 1'b1 : 1'b0;

endmodule

module limiter ( c, d, out1 ) ;
// You will probably want to flush out the nature of these port declarations:
   input reg [0:7] c;
   input reg [0:7] d;
   output reg [0:7] out1;

   // Implement the module here

always @*

if (d < c)
   begin
   assign out1 = 0;
   end
   else
   begin
   assign out1 = d;
   end
endmodule


module comp_x4 ( a, b, out4 ) ;
// You will probably want to flush out the nature of these port declarations:
   input real a;
   input real b;
   output real out4;

   // Implement the module here

always @*

if (a < b)
   begin
   assign out4 =0;
   end
   else
   begin
   assign out4 =5;
   end

endmodule

Credits

alainstas

70 projects • 37 followers

product marketing engineer at Vishay. began to simulate in spice programs in 2014.

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A simple PELTIER temperature controller in VERILOG/Qspice

Things used in this project

Hardware components

Software apps and online services

Story

Schematics

a simple verilog PWM temperature controller for Peltier

netlist of Vishay NTC NTCS0603 for Qspice

a variation of PWM verilog temperature controller for Peltier

Code

netlist for a peltier module in Qspice

simple PWM controller in verilog

Credits

alainstas

Comments

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A simple PELTIER temperature controller in VERILOG/Qspice

A simple PELTIER temperature controller in VERILOG/Qspice

Things used in this project

Hardware components

Software apps and online services

Story

Schematics

a simple verilog PWM temperature controller for Peltier

netlist of Vishay NTC NTCS0603 for Qspice

a variation of PWM verilog temperature controller for Peltier

Code

netlist for a peltier module in Qspice

simple PWM controller in verilog

Credits

alainstas

Comments

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