PID temperature controller as VERILOG module in Qspice

// Automatically generated .v file on Thu Dec  7 17:34:23 2023
//

module pid_verilog5_x8 ( prop1, diff1, integ1, clk1, vcc1, kp1, kd, ki, vpid1 ) ;
// You will probably want to flush out the nature of these port declarations:
   input real prop1;
   input real diff1;
   input real integ1;
   input reg clk1;
   input real vcc1;
   input real kp1;
   input real kd;
   input real ki;
   output real vpid1;

   // Implement the module here

always @(posedge clk1)
begin
assign vpid1 =(vcc1)- (kp1)*(prop1)- (kd) *(diff1) - (ki)*(integ1);
end
endmodule
// Automatically generated .v file on Fri Dec  8 19:16:08 2023
//

module pid_verilog6_x5 ( in, clk, out ) ;
// You will probably want to flush out the nature of these port declarations:
   input real in;
   input reg clk;
   output real out;

   // Implement the module here

integer out10;
integer out11;

deriveintegverilog_x3 myderive(in, clk, out10);
deriveintegverilog_x4  myderive2(out10,clk,out10,out11);
dac_x1 mydac(out11,clk,out);



endmodule



module deriveintegverilog_x3 ( in1, clk1, out1 ) ;
// You will probably want to flush out the nature of these port declarations:
   input real in1;
   input reg clk1;
   output integer out1;

   // Implement the module here
integer result1;
always @(posedge clk1) begin
    result1 = (in1)/5*37500;
    if (result1 > 37500) result1 = 37500;
    else if (result1 < -37500) result1 = 0;
end
assign out1 = result1;

endmodule


module deriveintegverilog_x4 ( a, clk2, b, out4 ) ;
// You will probably want to flush out the nature of these port declarations:
   input integer a;
   input reg clk2;
   output integer b;
   output integer out4;
initial out4=0;
   // Implement the module here
always @(posedge clk2) begin
   assign out4 = a*0.002 + out4;
end
endmodule

module dac_x1 ( in2, clk3, out2 ) ;
// You will probably want to flush out the nature of these port declarations:
   input integer in2;
   input reg clk3;
   output real out2;

   // Implement the module here
real result2;
always @(posedge clk3) begin
    result2 = (in2)*5/10000;
    if (result2 > 10000) result2 = 10000;
    else if (result2 < -10000) result2 = -10000;
end
assign out2 = result2;

endmodule
// Automatically generated .v file on Sat Dec  2 08:09:00 2023
//

module derivate2_x1 ( vin, clk1, clk2, vout ) ;
// You will probably want to flush out the nature of these port declarations:
   input real vin;
   input reg clk1;
   input reg clk2;
   output real vout;

   // Implement the module here
  // Implement the module here
reg [0:15] dvin1;
reg [0:15] dvin2;

adc_x1   myadc1(vin,clk1,dvin1);
adc_x1   myadc2(vin,clk2,dvin2);
comp_x4 mycomp(dvin2,dvin1,vout,clk2);

endmodule



module adc_x1 ( in, clk, out ) ;
// You will probably want to flush out the nature of these port declarations:
   input real in;
   input reg clk;
   output reg [0:15] out;

   // Implement the module here

integer result;

always @(posedge clk) begin
    result = (in)/5*37500;
    if (result > 37500) result = 37500;
    else if (result < -37500) result = -37500;
end

assign out = result;

endmodule

module comp_x4 ( a, b, out4 ,clk) ;
// You will probably want to flush out the nature of these port declarations:
   input integer a;
   input integer b;
   input clk;
   output real out4;
   real out5;

   // Implement the module here

always @(negedge clk) begin

   out5 = (b-a);
   if (out5 > 100) out5 =out4;
   else if (out5 <-100) out5 =out4;

   end
assign out4 = out5;
endmodule

// Automatically generated .v file on Mon Dec 11 14:38:29 2023
//

module pid_verilog7_x1 ( clkin, clkout ) ;
// You will probably want to flush out the nature of these port declarations:
   input reg clkin;
   output reg clkout;

   // Implement the module here
assign clkout = ~(clkin);

endmodule