PWM controller VERILOG in Qspice (with ADC and counter)

// Automatically generated .v file on Wed Sep 27 09:24:29 2023
//

module PWM_temp_controller_X1 ( in, clk, preset, vcc, out ) ;
// You will probably want to flush out the nature of these port declarations:
   input real in;
   input reg clk;
   input reg preset;
   input reg [0:7] vcc;
   output real out;

   // Implement the module here
reg [0:7]out2;
reg [0:7]out3;
adc_x1  myadc(in,clk,vcc,out2);
counter mycount(clk,preset,vcc,out3);
comp_x1 mycomp(out2,out3,vcc,out);

endmodule


module adc_x1(in, clk,vcc, out ) ;

   input real in;
   input reg clk;
   input real vcc;
   output reg[0:7] out;

integer result;

always @(posedge clk) begin
    result = -400 +  (in)/(vcc)*1000;
    if (result > 255) result = 255;
    else if (result < 0) result = 0;
end
assign out = result;
endmodule


module counter ( clk, preset, nibble, out ) ;

   input reg clk;
   input reg preset;
   input reg [0:7] nibble;
   output reg [0:7] out;


  always @(posedge clk or posedge preset)
   begin
      if(preset)
         begin
            out <=( nibble);
         end
      else
         begin
            out <= (out +  8'h01);
         end
   end

endmodule

module comp_x1 ( a, b,vcc, out ) ;

   input real  a;
   input real  b;
   input real vcc;
   output real out;

always @*
if (a < b)
   begin
   assign out =0;
   end
   else
   begin
   assign out = vcc;
   end

endmodule