alainstas
Published © GPL3+

PWM temperature control in Qspice with Verilog counter

This Qspice simulation is based on a Pulse Width Modulation NTC thermistor temperature control with the Ramp Voltage modelled in VERILOG

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PWM temperature control in Qspice with Verilog counter

Things used in this project

Hardware components

NTCS0603 SMD thermistor 10 Kohms +/-1%
Vishay NTCS0603 SMD thermistor 10 Kohms +/-1%
×1
Vishay VOT8125
×1
L0103M
×1

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Custom parts and enclosures

Qspice simulation for PWM temperature control

unzip and open in Qspice

Schematics

pwm_heating2_J9QumnXzne.zip

Code

netlist for thermistor NTCS0603 10K and VOT8125 from Vishay + triac littelfuse

Plain text
use it in Qspice
* Voltage_driven_thermistor
* $Revision History :correction <> introduced
* subckt for Qspice 21/08/2023
.SUBCKT NTCS0603E3103_LT RN Rp Ti Params:
* TOLR=0 TOLB=0
+ w=-10.510144466257
+ x=2816.74879403825
+ y=172444.245970535
+ z=-23248305.132252
+ gth=0.0031 gth1 = 0.00002
+ cth=0.0081
+ a=-10.4528701153889
+ r25=10000
+ b=1363.9319167994
+ c=1013209.19138484
+ d=-146294479.644505
+ T0=273.15
+ TR={1+TOLR/100}
+ TB={1+TOLB/100}
R_RTR    0  TR  {TR}
I_ITR    0 TR 1
R_RTB    0 TB  {TB}
I_ITB    0 TB  1
G_G1         AOUT 0 VALUE { if(V(Ti)>25,V(AOUT,
+  0)/(R25*V(TR)*exp(((D*V(TB)/(T0+abs(V(H))+V(Ti))+C*V(TB))/(T0+abs(V(H))+V(Ti))+B*V(TB))/(T0+V(Ti)+abs(V(H)))+A*V(TB))),0)
+  }
G_G2         AOUT 0 VALUE { IF(V(Ti)>25,0,V(AOUT,
+  0)/(R25*V(TR)*exp(((Z*V(TB)/(T0+abs(V(H))+V(Ti))+Y*V(TB))/(T0+abs(V(H))+V(Ti))+X*V(TB))/(T0+abs(V(H))+V(Ti))+W*V(TB))))
+  }
G_G3         H 0 VALUE {
+  if(V(Ti)>25,-V(RP,RN)*V(RP,RN)/(R25*V(TR)*exp(((D*V(TB)/(T0+abs(V(H))+V(Ti))+C*V(TB))/(T0+abs(V(H))+V(Ti))+B*V(TB))/
+  (T0+V(Ti)+abs(V(H)))+A*V(TB))),0)}
G_G4         H 0 VALUE {
+  if(V(Ti)>25,0,-V(RP,RN)*V(RP,RN)/(R25*V(TR)*exp(((Z*TB/(T0+abs(V(H))+V(Ti))+Y*V(TB))/(T0+abs(V(H))+V(Ti))+X*V(TB))/
+  (T0+V(Ti)+abs(V(H)))+W*V(TB))))}
G_G5         RP RN VALUE { V(RP, RN)/V(AOUT) }
G_G6         H 0 VALUE { V(H)*(Gth + Gth1*(V(Ti)-25)) }
I_I1         0 AOUT DC 1Adc
R_R1         0 AOUT  1T TC=0,0
R_R2         0 H  1T TC=0,0
C_C1         0 H  {Cth}
R_R99        0 Ti 1T
.IC V(H) =0
.ENDS
*
* Library of Phototriac Optocoupler VOT8125
* Copyright VISHAY, Inc. 2018 All Rights Reserved.

.SUBCKT VOT8125 A C NC MT2 NC MT1
X1         MT1 GATE MT2 VOT8125_tr
D1         10 C Demit
V3         11 10 0Vdc ; emitter current probe
R3         A 11  1u TC=0,0
R4	   0 NC 1MEG
C1	   0 NC 1u
G1         0 GATE VALUE { I(v3) * 1.05 }
.MODEL Demit d
+IS=5.60248e-15 RS=1.43261 N=1.58216 EG=1.3
+XTI=3.75582 BV=6 IBV=5e-6 CJO=1e-11
+VJ=0.7 M=0.5 FC=0.5 TT=1e-09
+KF=0 AF=1
.ENDS
**************
.SUBCKT VOT8125_tr  3 2 1
*     TERMINALS: MT1 G MT2
QN1  5 4 3  NOUT OFF
QN2 11 6 7  NOUT OFF
QP1 6 11 3  POUT OFF
QP2  4 5 7  POUT OFF
DF  4  5  DZ
DR  6 11  DZ
RF  4 6  60.0G
RT2 1 7  0.45
RH  7 6  18.75k
RGP 8 3  102
RG  2 8  998
RS  8 4  3.65k
DN  9 2  DIN
RN  9 3  855k
GNN  6 7 9 3 24.3u
GNP  4 5 9 3 26.5u
DP 2 10  DIP
RP 10 3  110k
GP  7 6 10 3 20.5u
.MODEL DIP D ( IS=1.07f N=1.50 )
.MODEL DIN D ( IS=1.07f )
.MODEL DZ D ( IS=1.07f N=1.5 IBV=10.0n BV=800 )
.MODEL POUT PNP ( IS=1.07f BF=5 BR=.1 CJE=35f TF=1.8u )
.MODEL NOUT NPN  ( IS=1.07f BF=20 BR=.1 CJE=35f CJC=67.0f TF=1.080u )
.ENDS

**************
**==================================================================*
* Note:                                                             *
* Although models can be a useful tool in evaluating device         *
* performance, they cannot model exact device performance           *
* under all conditions, nor are they intended to replace            *
* breadboarding for final verification!                             *
*                                                                   *
* Models provided by VISHAY Semiconductors GmbH are not             *
* as fully representing all of the specifications and operating     *
* characteristics of the semiconductor product to which the         *
* model relates.                                                    *
* The models describe the characteristics of typical devices.       *
* In all cases, the current data sheet information for a given      *
* device is the final design guideline and the only actual          *
* performance specification.                                        *
* VISHAY Semiconductors does not assume any liability arising       *
* from the model use. VISHAY Semiconductors reserves the right to   *
* change models without prior notice.				                *
**==================================================================*
|.SUBCKT L0103ME 1 2 3\nQnpn1 5 4 3 NoutF OFF\nQpnp1 4 5 7 PoutF OFF\nQnpn2 11 6 7 NoutR OFF\nQpnp2 6 11 3 PoutR OFF\nDfor 4 5 DZ OFF\nDrev 6 11 DZ OFF\nRfor 4 6 12MEG\nRon 1 7 300m\nRhold 7 6 250\nRGP 8 3 350\nRG 2 8 150\nRS 8 4 250\nDN 9 2 DIN OFF\nRN 9 3 6.0\nGNN 6 7 9 3 0.2\nGNP 4 5 9 3 2.0\nDP 2 10 DIP OFF\nRP 10 3 4.0\nGP 7 6 10 3 0.5\n.MODEL DIN D (IS=382F)\n.MODEL DIP D (IS=382F N=1.19)\n.MODEL DZ D (IS=382F N=1.5 IBV=50U BV=600)\n.MODEL PoutF PNP (IS=382F BF=1 CJE=190p TF=0.3U)\n.MODEL NoutF NPN (IS=382F BF=3 CJE=190p CJC=38p TF=0.3U)\n.MODEL PoutR PNP (IS=382F BF=5 CJE=190p TF=0.3U)\n.MODEL NoutR NPN (IS=382F BF=0.5 CJE=190p CJC=38p TF=0.3U)\n.ENDS

Credits

alainstas
69 projects • 37 followers
product marketing engineer at Vishay. began to simulate in spice programs in 2014.
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