Hackster is hosting Hackster Holidays, Finale: Livestream & Giveaway Drawing. Watch previous episodes or stream live on Tuesday!Stream Hackster Holidays, Finale on Tuesday!
alainstas
Published © GPL3+

Qspice ON /OFF temperature control simulation with NTC

A simulation is supplied in Qspice for an ON/OFF temperature control with a Vishay NTC thermistor, including a small VERILOG module

BeginnerProtip1 hour284
Qspice ON /OFF temperature control simulation with NTC

Things used in this project

Hardware components

NTCS0603 SMD thermistor 10 Kohms +/-1%
Vishay NTCS0603 SMD thermistor 10 Kohms +/-1%
×1

Software apps and online services

Qspice

Story

Read more

Custom parts and enclosures

On/OFF temperature control in Qspice with Vishay Thermistor

unzip and open in Qspice

Schematics

On/OFF temperature control in Qspice with Vishay Thermistor

unzip and open it in Qspice

Code

Netlist for a voltage/temperature driven NTC thermistor

Plain text
use it in a Qspice simulation
* Voltage_driven_thermistor
* $Revision History :correction <> introduced
* subckt for Qspice 21/08/2023
.SUBCKT NTCS0603E3103_LT RN Rp Ti Params: TOLR=0 TOLB=0
+ w=-10.510144466257
+ x=2816.74879403825
+ y=172444.245970535
+ z=-23248305.132252
+ gth=0.0031 gth1 = 0.00002
+ cth=0.0081
+ a=-10.4528701153889
+ r25=10000
+ b=1363.9319167994
+ c=1013209.19138484
+ d=-146294479.644505
+ T0=273.15
+ TR={1+TOLR/100}
+ TB={1+TOLB/100}
R_RTR    0  TR  1
I_ITR    0 TR 1
R_RTB    0 TB  1
I_ITB    0 TB  1
G_G1         AOUT 0 VALUE { if(V(Ti)>25,V(AOUT,
+  0)/(R25*V(TR)*exp(((D*V(TB)/(T0+abs(V(H))+V(Ti))+C*V(TB))/(T0+abs(V(H))+V(Ti))+B*V(TB))/(T0+V(Ti)+abs(V(H)))+A*V(TB))),0)
+  }
G_G2         AOUT 0 VALUE { IF(V(Ti)>25,0,V(AOUT,
+  0)/(R25*V(TR)*exp(((Z*V(TB)/(T0+abs(V(H))+V(Ti))+Y*V(TB))/(T0+abs(V(H))+V(Ti))+X*V(TB))/(T0+abs(V(H))+V(Ti))+W*V(TB))))
+  }
G_G3         H 0 VALUE {
+  if(V(Ti)>25,-V(RP,RN)*V(RP,RN)/(R25*V(TR)*exp(((D*V(TB)/(T0+abs(V(H))+V(Ti))+C*V(TB))/(T0+abs(V(H))+V(Ti))+B*V(TB))/
+  (T0+V(Ti)+abs(V(H)))+A*V(TB))),0)}
G_G4         H 0 VALUE {
+  if(V(Ti)>25,0,-V(RP,RN)*V(RP,RN)/(R25*V(TR)*exp(((Z*TB/(T0+abs(V(H))+V(Ti))+Y*V(TB))/(T0+abs(V(H))+V(Ti))+X*V(TB))/
+  (T0+V(Ti)+abs(V(H)))+W*V(TB))))}
G_G5         RP RN VALUE { V(RP, RN)/V(AOUT) }
G_G6         H 0 VALUE { V(H)*(Gth + Gth1*(V(Ti)-25)) }
I_I1         0 AOUT DC 1Adc
R_R1         0 AOUT  1T TC=0,0
R_R2         0 H  1T TC=0,0
C_C1         0 H  {Cth}
R_R99        0 Ti 1T
.IC V(H) =0
.ENDS

Verilog model of RS bistable with fail safe feature

Verilog
use it it in a Qspice simulation
// Automatically generated .v file on Sat Sep  2 10:42:28 2023
//

module rs_latchfs ( r, s, clk, fs, q, qbar ) ;
// You will probably want to flush out the nature of these port declarations:
   input reg r;
   input reg s;
   input reg clk;
   input reg fs;
   output reg q;
   output reg qbar;

   // Implement the module here
wire Q_int, Qn_int;

assign #1 Q_int = ~(s & Qn_int);
assign #1 Qn_int = ~(~r & Q_int);
assign q = (Q_int );
assign qbar = ~q | fs ;


endmodule

Credits

alainstas
67 projects • 35 followers
product marketing engineer at Vishay. began to simulate in spice programs in 2014.

Comments

Related channels and tags
  • Vishay