Design of a Test System for Polar Codes from DDC

Polar Codes are up to date topic. Thus it uses in 5G networks. So, we wanted to make our graduation project with Polar Codes. Last year a team in our school received a prize from thesame contest, they encouraged us so we wanted to do something new and walk in the field of FPGA. Whatever happens, we want to make a fully flexible, used controlled test system. We wanted to communicate with UART for this purpose. At the end of the project, we planned to create BER (Bit Error Rate) graphs.

Objectives

The aim of the test system is to test whatever you need. It means that you are not forced to use Polar Codes only. If you want to test another thing on FPGA you can test it just small definitions of IP Core and the rest are the same. Also in Polar Encoder and Polar Decoder parts, we want to make a polar encoder and decoder part very flexible. Flexible means that users can change any variable as message bits count, coding rate, binary erasure channel error probability, whenever they want. Also, we want to simulate BEC (Binary Erasure Channel) because it is defined in Erdal Arıkan’s and it is easier than AWGN (Additive White Gaussian Noise).

Features-in-Brief

● UART serial communication for remote controlling

● User-controlled parameters of Polar Encoder and Decoder

● Simulating Binary Erasure Channel

Project Summary

To sum up, after the completion of FPGA parts we wanted to start the benchmark runs using operation commands and receive results of the benchmark runs. As the outcome of the project, we wanted to create Bit Error Rate (BER) graphs using received results from FPGA and we wanted to see how close polar codes proposed for today’s popular technologies, like 5G networks, will achieve the bit rate performance of Shannon’s theoretical capacity limit. We implemented UART receiver, transmitter, and flexible Polar Encoder.

Design Overview

Channel coding basically employs a set of algorithmic operations on the original data stream at the transmitter, and another set of operations on the received data stream at the receiver to correct these errors. In this project, a test system for polar codes will be implemented on the Arty Z7 FPGA card using VHDL. We want to make our system very flexible. Flexible means that users can change any variable as message bits count, coding rate, binary erasure channel error probability whenever they want. So, we need to send commands to FPGA and receive outputs from FPGA. Due to fewer LEDs, switches on the Arty Z7 board we decided to use serial communications like UART. We implemented and tested the UART receiver and transmitter. For commands, we decided to create our own operating codes table. In UART, message bits counts are eight, so the first 4 bits are operation and the last 4 bits are relevant data for the selected operation. You can see the first version of the operation codes in Fig1.

Polar encoding is XOR operation according to some rules. It can be done static XORs for static message lengths but due to our flexibility mission, we use thetheG_Matrix method for encoding operation. Each 1 (one) in the G_Matrix shows XOR operation. You can see that G_Matrix for eight bits and relevant XOR scheme in Fig2.

And in Fig3, here is the simulation result of our Polar Encoder implementation. In our implementation G_Matrix calculated from scratch according to 8 bits. We checked the encoded data Erdal Arıkan who is the inventor of the Polar Codes and it is true.