Live Concert Improvement System from Digilent Design Contest

In order for sound engineers to be able to deliver high quality sound during a live event (for example a concert), sound recorded from all instruments is passed through a mixer, with which one can modify different sound parameters for each instrument (channel). Most venues have analog mixers (they are cheaper than digital versions) that require the sound engineer to stand near it in order to correct all the different details, and as such, he cannot hear exactly what the audience hears (since usually the sound equipment is placed somewhere on the side).

This project aims at giving mobility to sound engineers or even members of the band that is performing, by designing an add-on module for analog mixers that can be used to control some of the signal parameters.

This project will help sound engineers in live venues set signal parameters while being away from the physical mixer. This increased mobility will help him hear the sound from the audiences point of view and adjust accordingly.

The design is based on an Arty s7 fpga development board and the different peripherals required to connect the board to an audio mixer and a mobile device.

This design is modularly structured and as such parts of it can be used for other signal processing applications.

Our project was created with the goal of creating a fully functional, selling product. While that state is still far away, it remains a reasonable goal. It can also be used for academic purposes in both signal processing and HDL design classes.

While initially targeting the ArtyS7 board, this design can be ported to other FPGA based development boards, given they have the required number of pins.

Our design is based on the artyS7 FPGA board, and follows the diagram below:

The mobile phone (via bluetooth) is used to send commands and control the system both as a whole and per channel. Each channel processes audio data from the mixer independently of each other. Audio data comes through an analog to digital converter and following all the desired processing, goes back into the analog mixer through a digital to analog converter.

All modules have been designed in the Verilog hardware description language.

Detailed Design Description

Each processing block consists of an input stage (interfacing with ADC), an output stage (interfacing with DAC) and the actual processing stage. The processing stage itself is made up of multiple audio effects or desired functionalities. This architecture allows for easy adding of additional processing layers and as such is highly scalable.

The control processor (or the bt receiver) gives all the required information (if the submodule is active, internal register values) to each submodule via a simple address/data/we interface.

Each channel processing follows the diagram below:

Each processing block has an associated address range that selects internal registers used for controlling the submodule operation. Full address mapping will be centralized after all modules have been designed (for current implemented addresses see DEFINE.vh file).

Interfaces have been designed as finite state machines. An additional “sample now” command generator had to be created in order to control the sample rate of our audio signals (we have chosen the standard 48kHz).

All processing blocks have both sequential and combinational circuits and all of them can be bypassed or activated by configuring internal registers via the Bluetooth interface. The processing blocks are structured as shown below (diagram taken from gain processing block):

Using the control registers one can enable or disable the whole block and can set different values for all required computation parameters. Bypassing the block is achieved by using the demux/mux pair.

The gain block is achieved by multiplication and bit shifting since floating point operations are extremely hard to achieve on FPGAs.

Configuration commands can be sent through Bluetooth. Commands have the following structure: addr_MSByte + addr_LSByte + data_MSByte + data LSByte.

Main system clock is at 100MHz, all other necessary clocks being derived from it.