Programming RTL Accelerators via AXI Slave Wrappers

Introduction

In order to communicate to the accelerator from the PS (ARM) core on Zynq boards, we need to be able to talk to the accelerator via memory mapped registers. To do so we need to wrap our RTL interface into AXI slave interface which can be controlled from software. In this tutorial, we will learn the steps we need to take in Vivado as well as how we can program it from software via Vivado SDK.

Vivado: Hardware design steps

• Create a Vivado project
• Create block design & Add Zynq MPSoC

• Go to Tools / Create and Package New IP
• Choose Create a new AXI4 peripheral

• .Press NEXT until:

• For simple application, Lite is enough. It provides some registers for controlling an RTL accelerator

• Add IP sources (DO NOT ADD THROUGH IP Catalog in Project Manager as we would not be able to edit)

• Add TOP module into the block design and Run Block Automation
• Then Run Connection Automation (To create the interface, reset etc. connections)
• This results in a complete block design:

• Edit design as you want to use the registers you need:

• Save Design then Create HDL Wrapper (Let Vivado manage wrapper and auto-update)
• Perform Synthesis, Implementation and Bitstream Generation.
• Export Hardware with Bitstream + Launch SDK!

Vivado SDK: Programming your AXI Slave accelerator

Perform the following steps in the newly opened Vivado SDK:

• Modify bsp (Board Support Package) if needed for your boardFor Ultra96: change stdin/stdout to psu_uart_1 because pin out of Ultra96 is uart_1

• Check address mapping in here (This one is 0xA000_0000)It can also be seen in the vivado address manager window

• Create: File / New / Application ProjectEg: create Hello World project & modify later on

The below is just read and write to specific register we want (See attached code for complete example):

• To read simply deference the var pointing to accelerator address (*reg)

int val_of_reg = *reg;

• To write

*reg = val_to_assign;

• Config run and debug settings as:

Set the following options:

• Reset entire system
• Program FPGA
• Run psu_init (for booting up)
• PL Powerup

• Load and run