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We have planned to do Software Defined Radio by using FPGA. Firstly, we separated this project into two parts which are the transmitter part and receiver part. On the transmitter part we took sinusoidal wave data from MATLAB. By using these data, sinusoidal wave was implemented on FPGA board. As long as we have done this issue, araised cosine filter was created on FPGA by doing thesame process. Then, we made raised cosine filter arrays with data that was expected to come from themicrophone, but we created data by hand, we could not use microphone.
After that we multiplied Sinusoidal wave and raised cosine filter arrays. As final process for transmitter part we added these arrays each other and observed transmitting wave form by using an oscilloscope. On the receiver part, we could not do so much thing but sinusoidal wave and raised cosine filter are used in this part. We will make Phase-Locked Loop for catching transmitting signal correctly.
ObjectivesGenerally, analog radios have one modulation type and they can not be implemented new technology easily. It is necessary to change their hardware to adjust modulation type. Because of that, people who use these radios have to pay money to change. In addition, analog radios’ transmitters are very expensive and large. We solve these problems by implementing software define radio on FPGA. We have chosen FPGA since it works faster than other microcontroller thanks to working parallel processing.
With this project, we want to create new platform for communication. This platform will work all digitally, and it can be implemented new technology easily. For example, if new modulation type, that is faster than other modulation types, is made, we can change code and keep using software defined radio.
Another usage area is that you can broadcast by using software define radio which is made by us. This broadcast will be more safety then analog systems. Because of that, communication between planes, ships or any other means of transport is provided by SDR.
Features and SpecificationsBasically, sinusoidal signals and raised cosine filter are implemented on FPGA. We have implemented 4 QAM. In this method, data is separated two parts as imaginal and real. We have 8 bits data and this data is divided by twos. Four bits goes to one ROM and these represent imaginal part, other four bits goes to different ROM and these represent real part. These ROM are shown in Figure1. Raise cosine filter phase changes by data. If data bit is equal to 1, raised cosine is normal without any phase changing. If data bit is equal to 0 (normally it is equal to -1 but we chose like because it is easier), raised cosine is reverse with 180-degree phase changing. This raised cosine goes to their address (it is indicated figure 1). Finally, they are added each other and go to antenna.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
entity Tx_main is
Port ( clk,reset : in STD_LOGIC;
Tx_out : out STD_LOGIC_VECTOR (7 downto 0));
end Tx_main;
architecture main_flow of Tx_main is
component Multiplier is
Port ( A,B : in STD_LOGIC_VECTOR (7 downto 0);
D : out STD_LOGIC_VECTOR (7 downto 0));
end component;
--------------- Byte_Array definitions ------------------------
type Byte_Array is array(natural range <>) of std_logic_vector(7 downto 0);
constant sin_rom : Byte_Array(1023 downto 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constant cos_rom : Byte_Array(1023 downto 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constant RC_pos_rom : Byte_Array(1023 downto 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constant RC_neg_rom : Byte_Array(1023 downto 0): = ("00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000001","00000001","00000001","00000001","00000001","00000001","00000001","00000001","00000001","00000001","00000001","00000001","00000001","00000001","00000001","00000001","00000001","00000001","00000001","00000001","00000001","00000001","00000001","00000001","00000001","00000001","00000001","00000001","00000001","00000001","00000001","00000001","00000001","00000001","00000001","00000001","00000010","00000010","00000010","00000010","00000010","00000010","00000010","00000010","00000010","00000010","00000010","00000010","00000010","00000010","00000010","00000010","00000010","00000010","00000010","00000010","00000010","00000010","00000010","00000010","00000010","00000010","00000011","00000011","00000011","00000011","00000011","00000011","00000011","00000011","00000011","00000011","00000011","00000011","00000011","00000011","00000011","00000011","00000011","00000011","00000011","00000011","00000011","00000011","00000011","00000011","00000011","00000011","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000100","00000011","00000011","00000011","00000011","00000011","00000011","00000011","00000011","00000011","00000011","00000011","00000011","00000011","00000010","00000010","00000010","00000010","00000010","00000010","00000010","00000010","00000010","00000010","00000001","00000001","00000001","00000001","00000001","00000001","00000001","00000001","00000001","00000000","00000000","00000000","00000000","00000000","00000000","00000000","11111111","11111111","11111111","11111111","11111111","11111111","11111110","11111110","11111110","11111110","11111110","11111110","11111101","11111101","11111101","11111101","11111101","11111101","11111100","11111100","11111100","11111100","11111100","11111011","11111011","11111011","11111011","11111010","11111010","11111010","11111010","11111010","11111001","11111001","11111001","11111001","11111000","11111000","11111000","11111000","11110111","11110111","11110111","11110111","11110110","11110110","11110110","11110110","11110101","11110101","11110101","11110101","11110100","11110100","11110100","11110100","11110011","11110011","11110011","11110010","11110010","11110010","11110010","11110001","11110001","11110001","11110000","11110000","11110000","11101111","11101111","11101111","11101111","11101110","11101110","11101110","11101101","11101101","11101101","11101100","11101100","11101100","11101011","11101011","11101011","11101010","11101010","11101010","11101001","11101001","11101001","11101000","11101000","11101000","11100111","11100111","11100111","11100110","11100110","11100110","11100101","11100101","11100101","11100100","11100100","11100100","11100011","11100011","11100011","11100010","11100010","11100001","11100001","11100001","11100000","11100000","11100000","11011111","11011111","11011111","11011110","11011110","11011110","11011101","11011101","11011101","11011100","11011100","11011100","11011011","11011011","11011010","11011010","11011010","11011001","11011001","11011001","11011000","11011000","11011000","11010111","11010111","11010111","11010110","11010110","11010110","11010101","11010101","11010101","11010100","11010100","11010100","11010011","11010011","11010011","11010010","11010010","11010010","11010010","11010001","11010001","11010001","11010000","11010000","11010000","11001111","11001111","11001111","11001110","11001110","11001110","11001110","11001101","11001101","11001101","11001100","11001100","11001100","11001100","11001011","11001011","11001011","11001011","11001010","11001010","11001010","11001010","11001001","11001001","11001001","11001001","11001000","11001000","11001000","1100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---------------- Signals -------------------------------
signal i,j : std_logic_vector(9 downto 0):="0000000000";
signal j_clk : std_logic;
signal tx_up : std_logic_vector(7 downto 0);
signal tx_dw : std_logic_vector(7 downto 0);
signal RC_up : std_logic_vector(7 downto 0);
signal RC_up_1 : std_logic_vector(7 downto 0);
signal RC_up_2 : std_logic_vector(7 downto 0);
signal RC_up_3 : std_logic_vector(7 downto 0);
signal RC_up_4 : std_logic_vector(7 downto 0);
signal RC_dw : std_logic_vector(7 downto 0);
signal RC_dw_1 : std_logic_vector(7 downto 0);
signal RC_dw_2 : std_logic_vector(7 downto 0);
signal RC_dw_3 : std_logic_vector(7 downto 0);
signal RC_dw_4 : std_logic_vector(7 downto 0);
signal Data : std_logic_vector(7 downto 0);
constant Data_str : Byte_Array(7 downto 0):=(x"00",x"11",x"33",x"55",x"00",x"AA",x"DD",x"FF");
signal Up_Data : std_logic_vector(3 downto 0);
signal Dw_Data : std_logic_vector(3 downto 0);
signal indx : std_logic_vector(1 downto 0):="00";
signal index : std_logic_vector(2 downto 0):="000";
signal indx_clk : std_logic;
signal index_clk : std_logic;
signal sin : std_logic_vector(7 downto 0);
signal cos : std_logic_vector(7 downto 0);
begin
Upper_Multiplier: Multiplier port map(a => RC_up, b => cos, d => tx_up);
Lower_Multiplier: Multiplier port map(a => RC_dw, b => sin, d => tx_dw);
process(clk,reset)
begin
if reset = '1' then
i <= "0000000000";
elsif clk'event and clk='0' then
i <= i + 1;
elsif clk'event and clk='1' then
Tx_out <= tx_up + tx_dw+128;
end if;
end process;
j_clk <= i(5);
process(j_clk,reset)
begin
if reset = '1' then
j <= "0000000000";
elsif j_clk'event and j_clk='0' then
j <= j + 1;
end if;
end process;
indx_clk <= j(7);
process(indx_clk,reset)
begin
if reset = '1' then
indx <= "00";
elsif indx_clk'event and indx_clk='0' then
indx <= indx + 1;
if indx = "00" then
up_data(0) <= data(0);
dw_data(0) <= data(1);
elsif indx = "01" then
up_data(1) <= data(2);
dw_data(1) <= data(3);
elsif indx = "10" then
up_data(2) <= data(4);
dw_data(2) <= data(5);
elsif indx = "11" then
up_data(3) <= data(6);
dw_data(3) <= data(7);
end if;
end if;
end process;
index_clk <= indx(1);
process(index_clk,reset)
begin
if reset = '1' then
index <= "000";
elsif index_clk'event and index_clk='0' then
index <= index + 1;
end if;
end process;
data <= data_str(conv_integer(index));
sin <= sin_rom(conv_integer(i));
cos <= cos_rom(conv_integer(i));
RC_up <= RC_up_1 + RC_up_2 + RC_up_3 + RC_up_4;
RC_dw <= RC_dw_1 + RC_dw_2 + RC_dw_3 + RC_dw_4;
RC_up_1 <= RC_pos_rom(conv_integer(j)) when up_data(0)='1' else RC_neg_rom(conv_integer(j)) when up_data(0)='0' else "ZZZZZZZZ";
RC_up_2 <= RC_pos_rom(conv_integer(j+256)) when up_data(1)='1' else RC_neg_rom(conv_integer(j+256)) when up_data(1)='0' else "ZZZZZZZZ";
RC_up_3 <= RC_pos_rom(conv_integer(j+512)) when up_data(2)='1' else RC_neg_rom(conv_integer(j+512)) when up_data(2)='0' else "ZZZZZZZZ";
RC_up_4 <= RC_pos_rom(conv_integer(j+768)) when up_data(3)='1' else RC_neg_rom(conv_integer(j+768)) when up_data(3)='0' else "ZZZZZZZZ";
RC_dw_1 <= RC_pos_rom(conv_integer(j)) when dw_data(0)='1' else RC_neg_rom(conv_integer(j)) when dw_data(0)='0' else "ZZZZZZZZ";
RC_dw_2 <= RC_pos_rom(conv_integer(j+256)) when dw_data(1)='1' else RC_neg_rom(conv_integer(j+256)) when dw_data(1)='0' else "ZZZZZZZZ";
RC_dw_3 <= RC_pos_rom(conv_integer(j+512)) when dw_data(2)='1' else RC_neg_rom(conv_integer(j+512)) when dw_data(2)='0' else "ZZZZZZZZ";
RC_dw_4 <= RC_pos_rom(conv_integer(j+768)) when dw_data(3)='1' else RC_neg_rom(conv_integer(j+768)) when dw_data(3)='0' else "ZZZZZZZZ";
end main_flow;
Appendix B: Upper Multiplier
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
entity Multiplier is
Port ( A,B : in STD_LOGIC_VECTOR (7 downto 0);
D : out STD_LOGIC_VECTOR (7 downto 0));
end Multiplier;
architecture Logic_Flow of Multiplier is
signal A_mag : STD_LOGIC_VECTOR (7 downto 0);
signal B_mag : STD_LOGIC_VECTOR (7 downto 0);
signal sign : STD_LOGIC;
signal D0,D1,D2,D3,D4,D5,D6,D7,Dtot,Dtotn : STD_LOGIC_VECTOR(15 downto 0):=x"0000";
--signal Dpos,Dneg : STD_LOGIC_VECTOR(7 downto 0);
begin
A_mag <= '0' & A(6 downto 0) when A(7)= '0' else not A + 1;
B_mag <= '0' & B(6 downto 0) when B(7)= '0' else not B + 1;
sign <= A(7) xor B(7);
D0(7 downto 0) <= A_mag when B_mag(0)='1' else x"00";
D1(8 downto 1) <= A_mag when B_mag(1)='1' else x"00";
D2(9 downto 2) <= A_mag when B_mag(2)='1' else x"00";
D3(10 downto 3) <= A_mag when B_mag(3)='1' else x"00";
D4(11 downto 4) <= A_mag when B_mag(4)='1' else x"00";
D5(12 downto 5) <= A_mag when B_mag(5)='1' else x"00";
D6(13 downto 6) <= A_mag when B_mag(6)='1' else x"00";
D7(14 downto 7) <= A_mag when B_mag(7)='1' else x"00";
Dtot <= D0 + D1 + D2 + D3 + D4 + D5 + D6 + D7;
Dtotn <= not Dtot +1;
D <= x"00" when A=x"00" or B=x"00" else '0' & Dtot(14 downto 8) when sign='0' else '1' & Dtotn(14 downto 8);
--Dpos <= '0' & Dtot(14 downto 8);
--Dneg <= not Dpos + 1;
--D <= Dpos when sign = '0' else Dneg;
end Logic_Flow;
Appendix C: Lower Multiplier
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
entity Multiplier is
Port ( A,B : in STD_LOGIC_VECTOR (7 downto 0);
D : out STD_LOGIC_VECTOR (7 downto 0));
end Multiplier;
architecture Logic_Flow of Multiplier is
signal A_mag : STD_LOGIC_VECTOR (7 downto 0);
signal B_mag : STD_LOGIC_VECTOR (7 downto 0);
signal sign : STD_LOGIC;
signal D0,D1,D2,D3,D4,D5,D6,D7,Dtot,Dtotn : STD_LOGIC_VECTOR(15 downto 0):=x"0000";
--signal Dpos,Dneg : STD_LOGIC_VECTOR(7 downto 0);
begin
A_mag <= '0' & A(6 downto 0) when A(7)= '0' else not A + 1;
B_mag <= '0' & B(6 downto 0) when B(7)= '0' else not B + 1;
sign <= A(7) xor B(7);
D0(7 downto 0) <= A_mag when B_mag(0)='1' else x"00";
D1(8 downto 1) <= A_mag when B_mag(1)='1' else x"00";
D2(9 downto 2) <= A_mag when B_mag(2)='1' else x"00";
D3(10 downto 3) <= A_mag when B_mag(3)='1' else x"00";
D4(11 downto 4) <= A_mag when B_mag(4)='1' else x"00";
D5(12 downto 5) <= A_mag when B_mag(5)='1' else x"00";
D6(13 downto 6) <= A_mag when B_mag(6)='1' else x"00";
D7(14 downto 7) <= A_mag when B_mag(7)='1' else x"00";
Dtot <= D0 + D1 + D2 + D3 + D4 + D5 + D6 + D7;
Dtotn <= not Dtot +1;
D <= x"00" when A=x"00" or B=x"00" else '0' & Dtot(14 downto 8) when sign='0' else '1' & Dtotn(14 downto 8);
--Dpos <= '0' & Dtot(14 downto 8);
--Dneg <= not Dpos + 1;
--D <= Dpos when sign = '0' else Dneg;
end Logic_Flow;
Baran BOZKURT, Aydın Kaan DURUKAN & Muhammed Cevat ÇAKICI
Posted by 
Alex Wong
Alex Wong
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