Vitis 2023.2 AXI4-Lite Slave Custom RTL

Zynq SoC has two parts: PL and PS. Programable Logic is equivalent to what we know as FPGA and Processing System is simply an ARM microprocessor. Imagine a board which has STM32 MCU and ARTIX7 FPGA where ARTIX7 and STM32 are connecting via UART. In Zynq we have the best of both worlds in a single chip. AXI is the interface between PL and PS inside Zynq. We can simply write our own RTL code and connect it to processor via Xilinx-delivered IP such as AXI GPIO. It's very straightforward and there is no need to change your HDL code to support AXI.

But more professional job is to package your RTL codes as AXI-Lite peripherals. It's not only about doing things better, for some applications, you need to use two other types of AXI: AXI Full and AXI Stream.Let's open Vivado 2023.2 and start this simple example. Stage 1: 1. Vivado -> Project -> New and enter project name and location.2. Select RTL Project and tick the box "Do not specify the sources at this time"

3. Select "ZedBoard Zynq..." in the Boards tab search for zedboard in the Search field and the press Refresh button. Install zedboard by pressing the install icon in Status column.

Stage 2: 1. Vivado -> Tools -> Create and Package New IP... then click Next>2. Select Create a new AXI4 peripheral

3. Write Name and Description for LED in Peripheral Details window.

4. Adding Interfaces needs to know a few things: 4.1 Interface could be Lite, Full or Stream, for this example we use Lite

4.2 Our LED Peripheral will act as a slave that we send a byte of data from processor to it. We write and read from the register in AXI peripheral the minimum numbers for registers are 4 and data width is 32 which more than enough for our 8 LEDs.

4.3 These 4 registers are named slv_reg0 to slv_reg3.

5. In last step of wizard select Edit IP and then Finish.

6. New Vivado project will be opened with two VHDL code as follow:

7. Open the submodule named xxx _S00_AXI.vhd then add led 8-bit output port:

-- Users to add ports here
          LED : out std_logic_vector(7 downto 0);
-- User ports ends

8. Scroll to the end of file and assign 7 LSBs of slv_reg0 to LED output:

-- Add user logic here
LED <= slv_reg0(7 downto 0);
-- User logic ends

9. Open the top module and add LED output port for the module and component and then port map them together.

10. Save VHDL codes and then open comonent.xml from Sources window in Vivado

11. From Packing Steps do the following:File Groups -> Merge changes from File Group Wizard Customization Parameters -> Merge changes from Customization Parameters WizardReview and Package -> IP has been modified Review and Package -> Re-Package IP

Stage 3: After Packaging IP, the Vivado project for editing IP is closed and we back to main project.

1. In Flow Navigator part, in IP INTEGRATOR, click on "Create Block Design", enter a Design name, and press OK.

2. In Diagram window click the plus (+) icon to Add IP. Search for "ZYNQ7 Processing System", then press enter to place it in Diagram window.

3. Again, click the plus (+) icon and search for led IP and place it.

4. Click Run Connection Automation from narrow green bar to automatically connect LED IP to Zynq Processing System and then OK without any changes.

5. Select output port of IP and press Ctrl+T to Make it External.

6. Since you've selected a board (ZedBoard) not just an FPGA, the "Run Block Automation" will be appeared on green narrow. Click Run Block Automation: tick Apply Board Preset and Disable both "Cross Trigger In" and "Cross Trigger Out".

7.Validate Design by pressing F6 or its icon. You have to see Validation successful.

8. To create HDL Wrapper, in BLOCK DESIGN window, Source tab, right click on the name of Block Design, and select "Create HDL Wrapper...".

(Follow BLOCK DESIGN ->Source -> Design Source -> zedboard name.db -> right click -> Create HDL Wrapper...)

Then, in Create HDL Wrapper window, select "Let Vivado manage wrapper and auto-update", and press OK.

9. Flow Navigator -> RTL ANALYSIS -> Run LinterThe run linter is a Vivado built-in features which analyzes the RTL design code, detect design errors and provides a detailed report for the violations.

10. Flow Navigator -> RTL ANALYSIS -> Open Elaborated DesignIn I/O Ports you have to connect 8 LEDs port to the FPGA pin for LEDs on Zedboard. If you don't see I/O Ports tap from Layout menu select I/O Planning.

11. Select I/OStd as LVCMOS33 and add Package Pin according to Zedboard user guide of from the silkscreen test for LEDs on board.

Press Ctrl + s to save the XDC file.

12. Flow Navigator -> PROGRAM AND DEBUG -> Generate Bitstream.13. Final step in this stage, is exporting the hardware. Follow File -> Export -> Export Hardware. Then press Next. Having RTL code for FPGA, we have to select Include bitstream. Enter XSA file name and the directory.

Stage 3: Creating Platform

1. Launch Vitis -> Open Workspace It is recommended to create a folder with the name of Vitis in the directory of Vivado Project. Then browse and select this folder. Create Platform Component in Embedded Development in Welcome tab. Enter component name and the location.

2. Browse the .xsa file from Vivado project. Then press Next.

3. Here, you should select OS and Processor. The selections of Operating system are standalone, FreeRTOS and Linux. Select standalone and press Next.

4. To ascertain everything is OK, Build the platform just created.

Stage 4: Creating Application

1. You can create an application by clicking on Create Embedded Application in Embedded Development part or using Examples from Welcome tab.

2. Click on Hello World in Embedded Software Examples, then press "Create Application Component from Template".

3. Enter component name and location, then Select platform from the created platforms, then press Next.

Stage 5: Software Programming

1. Open drop-down menu of the project (named hello_world) in VITIS, open Source, then click helloworld.c. (As Hello World template is used to create this application, its name is helloworld.c.)

2. Add header files:

#include "xparameters.h"
#include "sleep.h"

3. Open the xparameters.h and find the base address of AXI_LED_RTL

4. Replace the main function with the following code:

UINTPTR led;
int main()
{
init_platform();
led = XPAR_AXI_LED_RTL_0_BASEADDR;
Xil_Out32(led, (u32) 15);
cleanup_platform();
return 0;
}

5. Connect Programmer to the board.6.Build the program.7. After building completed, Run will be active. Click Run.Since we write 15 = 0x00001111 to the RLT logic first 4 LEDs on Zedboard must turn on.