Debraj Das
Created October 8, 2020 © MIT

Image compression in FPGAs using Xilinx DPUs

Designing an autoencoder based compression technique to compress images at near realtime 30 fps.

BeginnerFull instructions providedOver 1 day51
Image compression in FPGAs using Xilinx DPUs

Things used in this project

Hardware components

Ultra96-V2
Avnet Ultra96-V2
This was used along with the Power supply and the SD Card.
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Software apps and online services

Ubuntu 18.04.1
PetaLinux
AMD PetaLinux

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Schematics

Essentials for carrying out image processing on Ultra96V2

This project does not require any extra devices, and complete processing is within the Ultra96V2, hence no additional schematic is needed. However, if one wishes one can attach a webcam to feed the information to the Ultra96V2

Code

CAE Based Image Compression

The model is trained and generated through the Jupyter Notebook. Which must be used using vitis ai docker file for processing and deployment.

Credits

Debraj Das

Debraj Das

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