Wideband Trans-impedance Amplifier Design - Optical Receiver

1. Introduction and Literature Search

Trans-impedance amplifier is an important block at the input of an optical receiver. They are an integral part of optical fiber receivers because they must sense the current produced by a photodiode, eventually generating a voltage that can be processed by subsequent circuits. The TIA amplifies the current of the receiver photodiode often called photocurrent and converts it to a voltage. TIAs are usually designed as wideband amplifiers to support the modulation bandwidth of the received optical signal.

There are several considerations while designing a TIA with respect to the vast number of topologies that could be implemented. The easiest and a passive topology one could think of is a resistive circuit, where the input current is applied over a large resistor and the gain observed is represented as a resistance which represents the output voltage to input current ratio. Another commonly used active topology is a Common-Gate amplifier as the first stage of the Trans-Impedance amplifier. In this, the current source is applied over the source of the CG amplifier and the output voltage of this stage is given as input to the gain stages of the TIA. An interesting topology is a Common-Source amplifier with a negative resistive feedback circuit. This sort of input stage design offers low input resistance and high bandwidth which are desired features of a TIA.

The project requires high trans-impedance gain, along with a high bandwidth and low noise to drive a very low differential output load impedance while consuming low power(<25mW). These performance requirements and parameters motivate the usage of multiple topologies and differential amplifier stages to achieve the high gain and output swing aspects from the TIA.

2. Process Characterization

a. Hand Calculations

b. Simulation Results(NMOS)

The first step in designing any analog system is to characterize the devices offered in the fabrication technology.

• ID vs VDS for 0<VDS<3V (L=600nm and W = Wn : {5um, 10um, 20um, 40um, 80um})

Comparing these results to the hand calculations indicate consistency, where the device is initially in triode region as IDS increases exponentially. Then it enters saturation region where the value of IDS gets constant for all values of VDS. It can be seen that as VGS is increased, the drain current increases.

• Vth vs ID for 0<ID<20mA (L=600nm and W = Wn : {5um, 10um, 20um, 40um, 80um})

Comparing these results to my hand calculations, indicate certain level of difference in the interpretation. As per hand calculations, VTH was solely dependent on the device width and independent of drain current IDS. But as per the simulation results, VTH varies quickly for drain currents less than 3mA. This effect might be because of the change in VTH due to increase in VDS. But when the device enters saturation, the threshold voltage remains constant.

• gm vs ID for 0<ID<20mA (L=600nm and W = Wn : {5um, 10um, 20um, 40um, 80um})

Hand calculations indicate that device transconductance is directly proportional to the square root of the (W/L) aspect ratio times the drain current, IDS so as W increases, the gm increases. So the simulation results are tallying with the hand calculations performed.

• Cgs and Cgd vs W for 4um<W<400um

Cadence uses SPICE matrix to calculate Cgs and Cgd and hence the negative relationship is observed between the capacitances and device width, W. Hand calculations indicate the same behavior of Cgs and Cgd on the positive axis which are in sync with the results obtained.

• Process fT

It can be observed here that there is no effect of varying widths which might imply that the current IDS doesn’t affect the process fT. . As per hand calculations, process fT is directly proportional to the gm and inversely proportional to Cgs and Cgd values. As Cadence derives a negative relationship for Cgs and Cgd , the results for process fT also show negative of what the hand calculations indicate.

b. Simulation Results(PMOS)

• ID vs VDS for -3V<VDS<0V (L=600nm and W = Wp : {5um, 10um, 20um, 40um, 80um})

• Vth vs ID for 0<ID<20mA (L=600nm and W = Wp : {5um, 10um, 20um, 40um, 80um})

• gm vs ID for 0<ID<20mA (L=600nm and W = Wn : {5um, 10um, 20um, 40um, 80um})

• Cgs and Cgd vs Wp for 4um<W<400um

• Process fT

3. Design Strategy

The following design has been considered after considering the requirements of high gain, high bandwidth, low noise and high output voltage swing while maintaining low power consumption:

• This design contains a multistage implementation with an NMOS Common Source Amplifier with a negative resistive feedback and PMOS Current Source Load in parallel with a PMOS Diode Connected Load as the 1st stage of the TIA. The CS Amplifier with negative feedback offers bandwidth extension in comparison with commonly used Common-Gate inputs to the TIA. The diode connected load offers higher bandwidths as opposed to using a resistive load. (As per Razavi – Design of Analog CMOS Integratd Circuits)
• The second stage is a differential amplifier converting a single ended output into a double ended output. This amplifier stage involves the usage of PMOS current source loads in parallel with PMOS diode connected loads with equal widths and device parameters on both sides making it a perfectly symmetric
• The third stage is a high gain stage which is a PMOS Common Source Amplifier with negative resistive feedback and a NMOS diode connected load. This stage was added upon simulating the circuit and identifying the requirement of gain after 2 stages. This stage’s amplifiers on both the negative output side and the positive output side are equally designed so their effect on the final bandwidth, gain and noise will remain the same. Decoupling capacitor and bias resistors have been used in between the 2nd and 3rd stages to have an effect on bandwidth while keeping the gain constant. The gain is mainly influenced by the PMOS stage.
• The fourth stage is also a PMOS Common Source Amplifier with negative resistive feedback and a NMOS diode connected load. Decoupling capacitor and bias resistors have been used again similar to previous stage to control the final bandwidth. This stage gives a low gain due to the output impedance of 300 Ω, but drives the output voltage and gives a high swing.

Parametric analyses were performed for all the stages to identify the values of bias resistors, decoupling capacitors and device widths. First the resistors are identified so as to operate the MOSFETs in saturation. After one of the bias resistor is finalized, the transimpedance gain – bandwidth plot is observed to identify the best value of the second bias resistance which gives both high gain and BW. Fixing these values, the next step was to run a parametric analysis to investigate the device width that would offer the best gain-BW product. Finally, the decoupling capacitor is calculated with all the values of Rup, Rdown, Wn finalized and fixed to offer the highest possible gain and BW requirements while keeping the output power consumption nominal. (As shown below)

4. Hand Calculations

5. Cadence Simulation Results

A. DC Operating Points (Voltages Annotated on the Schematic) Summary Table

B. AC Simulation

C. Transient Simulation

D. Noise Simulation

The input referred noise shown in this picture above is the input referred current noise spectral density equal to 3.47978e-16A. The input referred current noise observed was 18.6541nA.

E. Stability Analysis

F. Comparison Table (Performance Analysis)

6. Comparison of hand calculations and simulations

The differences observed between hand calculations and simulation results are caused due to the process variables utilized by Cadence. Cadence uses advanced modelling parameters for nmos4 and pmos4 technologies and hence the hand calculations vary slightly due to changes in the equations of drain current, transconductance etc.

In stage 1 of the TIA – NMOS CS Amplifier with negative resistive feedback and PMOS diode connected and current source load, the transimpedance gain as per the hand calculations for a Resistive feedback of Rf = 20kΩ is around 30kΩ. But the Cadence simulation results show a TI gain of 15kΩ. Also, the assumptions considered for the values of ƛ(lambda) in the calculation of drain current may not be seen matching with the considerations taken by Cadence.

Hand calculations helped in identifying how the TIA might be designed rather than completely designing it. It served as a first step in understanding what components / topologies offered what kind of gain bandwidth combinations. Cadence simulations provided a comprehensive outlook on the same ideas that were implemented through the various sorts of analysis methods that are available.

7. Conclusion

Design of TIA amplifier usually involves restrictions on the gain, bandwidth and power consumption parameters. And these performance parameters are achieved through the usage of negative feedback which provided a way to play with the gain-bandwidth product while keeping the overall stability high and noise low. The literature search really helped in picking these strategies and topologies and implementing them in my TIA design.

8. References

[1] Design of CMOS Analog Integrated Circuits by Behad Razavi

[2] Analog Integrated Circuit Design by Carusone

[3] https://www.hackster.io/13453/wide-band-transimpedence-amplifier-880511