FPGAPS

12 Projects18 Followers1 Following
Bio

Passionate About FPGA&Processing System Design | Sharing Expertise & Fostering Innovation | Provide training courses | Personalized support

Joined

July 2024

Location

Canada

Projects
How to configure, and validate a FFT IP core in Vivado using various test signals
FFT IP Core Tutorial: Vivado Simulation with Complex Numbers
456
Generate three signals with DDS compiler and implement lowpass filter in Vivado. The lowpass filter will filter the faster signal.
FPGA DSP: FIR Filter with DDS Compiler in Vivado
427
Learn how to implement a Numerically Controlled Oscillator (NCO) using CORDIC IP in Vivado!
CORDIC IP Tutorial: Create a NCO for Sine-Cosine Generation
304
Implement a sine wave generator on a ZCU104 board using block memory as a lookup table and clocking wizard, result demonstration with ILA
Dual-Frequency Sine Generator with LUT and ILA Debugging
168
Create a dual-core ARM application using Xilinx's Vivado and Vitis tools to control programmable logic (PL) with both A53 and R5 processors.
Dual Arm core hello world: control the PL using A53 and R5
372
PYNQ AXI GPIO and Memory Mapped IO (MMIO) Example: ARM Core Read User DIP Switch in Polling Mode and Control Circular Blinking LEDs status
PYNQ AXI GPIO & MMIO: Control Blinking LEDs With DIP Switch
103
Using AXI GPIO blocks for LED control and DIP switch input in Vivado use memory-mapped I/O with C pointers to access peripherals in Vitis
AXI GPIO, Memory-Mapped I/O MMIO, Read/Write Using C Pointer
860
Making a project in Vivado that contains both PL and PS side. Export XSA to Vits, make Hello World application with demonstration of result
Zynq Ultrascale+ Hello World in Vivado and Vitis
521
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