Pulse Modulation Techniques with the Analog Discovery 2

Introduction and Setup

This project is designed to explore a technique called Pulse Modulation that is used in digital to analog conversion (DAC). There are many types of signal modulation (both analog and digital), but we will be looking into two popular techniques in DAC called Pulse Width Modulation (PWM) and Pulse Density Modulation (PDM). Using the Analog Discovery 2 and Waveforms, we can generate these types of signals and analyze how a Low Pass Filter (LPF) is used to convert these carrier signals into an approximated sinusoidal signal.

To make the setup easier so you can get to the good stuff quicker, prefabricated workspaces for WaveForms are provided for download under the "Schematics" section for this project. The LPF we will be using is a 10k ohm resistor in series with a 10nF capacitor to ground. Place Channel 1 of the oscilloscope to read the voltage across the series combination of the resistor and capacitor and Channel 2 across only the capacitor. This will correspond to input and output voltages, respectively. DIO10 from the Analog Discovery 2 will be providing our input signal, so connect that to the resistor node not connected to the capacitor. Place a ground connection at the capacitor node that is not connected to the resistor and your hardware is all set up! Pictures of my setup are provided for reference below.

Brief Background

Digital signals can be described as being either "high" or "low" at any given time (or on and off). A pulse is a digital signal that alternates or switches between these high and low values in some manner. The relationship between time spent high and time spent low is called the duty cycle and is usually expressed as a percentage or fraction of the time the signal is high in relation to the period of the signal. A modulating pulse signal is a pulse that has a dynamic duty cycle, frequency, or both. A low pass filter takes advantage of this by essentially creating (for some specific moment in time) a voltage that is proportional to the instantaneous duty cycle. Over some time interval, the low pass filter outputs a voltage that is representative of the dynamics of the pulse duty cycle. This is usually done such that the output signal approximates a sinusoid or some other "curved" or "smooth" signal. In this project, this is due to the charging and discharging of our capacitor through our resistor. And thus, in a tiny nutshell, digital to analog conversion!

Pulse Width Modulation

The most commonly applied form of pulse modulation is Pulse Width Modulation. A PWM signal has a constant frequency but a changing duty cycle, which can be perceived as a changing "width" of the high voltage level. A PWM modulator usually consists of a register, binary counter, and a digital magnitude comparator. An n-bit binary counter counts 2^n values before rolling over. With a clock frequency of F_clock = 1 / T_clock Hz, the carrier frequency is a constant value F_carrier = F_clock / 2^n Hz. The n-bit register can store any binary value from 0 to (2^n) - 1. The comparator outputs a “high” as long as the counter value is lower than the register value and a “low” for the remainder of the carrier period. The “high” pulse length range is T_clock * [0 to (2^n) - 1] seconds, and likewise, the duty cycle is modulated with a range of [0 to (2^n) - 1] with a resolution of 2^(-n). Below is an example of eight PWM pulse signals with n = 3, a resolution of 1/8, and each line at different duty cycle (7/8 for MSB, 6/8 for bit 6, …, 1/8 for bit 1, 0 for LSB):

Download and open Waveforms Workspace 1 after you have set up your LPF then click run on Patterns 1 and Scope 1. In the oscilloscope view on top, you will see a digital PWM signal in orange and the demodulated, analog signal in blue. If you decrease the base time interval, you can get a look at the PWM signal.

In WaveForms Workspace 1, the PWM Pattern Generator (Patterns 1) instance uses a custom bus and two ROM logic units (we won't go into ROM logic here, but for more info about ROM logic, see the ROM logic attachment written by Mircea Dabacan):

• The 5-bit custom Bus1 (DIO9…DIO5). The bus values were imported from a.csv file, representing 100 samples of a sine period, scaled in the range 1 to 31, with the mid value of 16. Sampled at 100 kHz, this bus generates a 1 kHz sine approximation. The samples are used as the register described in the beginning of this section section.

• The 5-bit ROM logic block, ROM1. The truth table implements a 5-bit binary counter. Running at 500 kHz, it generates a carrier frequency of Fc = 500 kHz / 2^3.

• The 5-by-5-bit “greater than” comparator, ROM2. The truth table implements a comparator, with the output DIO10 = “high” whenever the register value is higher than the counter content. Running at 500 kHz, it generates a new comparison result for each state of the counter.

Take a look at the FFT window below the scope window in Scope 1 and the spectrum analyzer window Spectrum 1 for later comparison.

Next, download and open WaveForms Workspace 2. Run it just like you did with WaveForms Workspace 1 and compare the differences and similarities in Scope 1 and Spectrum 1. In this workspace, ROM1 and ROM2 are operating and a much higher frequency of 4MHz. What can you say about the conversion resolution? How do the FFT and Spectrum plots compare?

Pulse Density Modulation

Another popular pulse modulation technique is Pulse Density Modulation (PDM), also called sigma-delta modulation. PDM modulates both the frequency and the duty cycle of a pulse. Because of this, the duty cycle is also proportional to the instantaneous value of the modulator.

A PDM modulator usually consists of a register and an accumulator adder with carry output. The n-bit register can store any binary value from 0 to (2^n) - 1. Each clock period, the register content is added on top of the accumulated value. The carry out (overflow of the n-bit accumulator) is the output, modulated signal. It is “high” as often as the accumulator overflows, showing that a quanta, or “delta” resulted in the accumulation process. The “high” pulse is only 1 clock period long, but more “high” pulses can succeed when the register content is close to maximum. The concatenated “high” pulse length range is T_clock * [0 to (2^n) - 1], and the duty cycle can be modulated in the range of [0 to (2^n) - 1], with a resolution of 2^(-n).

For the same clock frequency and the same n-bit register length, the pulse width and duty cycle range and resolution are the same for PWM and PDM respectively. The difference consists in the way the “high” pulses are distributed over time. Below is an example of different PDM signals with n=3, resolution of 1/8, and each line at a different duty cycle (7/8 for MSB, 6/8 for bit 6, …, 1/8 for bit 1, 0 for LSB):

Notice that at highest and lowest duty cycles, the signals are identical to the PWM ones. For intermediate duty cycle values, the signals differ. Signal 2 has the same duty cycle as in the case of PWM, but the two clock periods with modulated signal “high” are not adjacent as is for the PWM signal. Instead, they are distributed in the 8 clock period sequence. The result is that the apparent carrier frequency is double for the same PWM signal. The biggest difference is at the midscale (signal 4). It has the same duty cycle as the corresponding PWM signal, but instead of 4 * T_clock adjacent “high” and “low” values, it alternates for each T_clock. This results in an apparent carrier frequency 4 times higher as compared to PWM.

Two advantages result: one, the carrier spectral components are at much higher frequencies making the LPF more efficient; and second, each modulated value exhibits a different apparent carrier frequency. The high frequency energy is spread out in the spectrum, making it easier to attenuate the noise level.

Go back to WaveForms Workspace 1, run Pattern 2, and analyze the oscilloscope window.

The PDM Pattern Generator (Patterns 2) instance uses a custom bus and one ROM logic unit (for more info about ROM logic, see the ROM logic attachment):

• The 5-bit custom Bus1 (DIO9…DIO5) is identical to the one used with PWM. The bus values were imported from a.csv file, representing 100 samples of a sine period, scaled in the range 1 to 31, with the mid value of 16. Sampled at 100kHz, this bus generates a 1kHz sine approximation. The samples are used as the register described earlier in this section.

• The 6-bit ROM logic block, ROM1. The truth table implements a 6-bit binary accumulator adder, with DIO10 as overflow. Running at 500kHz, it generates a new overflow result every 2 microseconds.

Take a look at the FFT window below the scope window in Scope 1 and the spectrum analyzer window Spectrum 1 for later comparison.

Next, download and open WaveForms Workspace 2. Run it just like you did with WaveForms Workspace 1 and compare the differences and similarities in Scope 1 and Spectrum 1. In this workspace, ROM1 is operating and a much higher frequency of 4MHz. What can you say about the conversion resolution? How do the FFT and Spectrum plots compare? How does the PDM compare to that of the PWM from Patterns 1?

From a visual standpoint, it seems that PDM can be much more efficient than PWM at the same clock speeds and resolution.