Juan Abelaira

7 Projects19 Followers6 Following
Bio

Electronics engineer focused on FPGA for accelerated computing and ML but with a wide background in electronics design and software design

Joined

November 2019

Skills

VHDL, Verilog, HLS, FPGA, Petalinux, Embedded software, RTOS, SDSoC, Zynq

Location

Basingstoke, United Kingdom

Projects
The FadNET neural network produces depth estimation from stereo images and can be used for SLAM (Simultaneous Localization and Mapping)
Depth estimation with AI and stereo vision on the KR260
23
Hands on tutorial on the creation of a sw platform and example of application accelerated in FPGA using a previously developed hw platform
Acceleration on KR260 with Vitis 24.2 (2)
181
Hands-on tutorial on building a Vivado (24.2 release) hardware platform for the KR260 board to be used with the Vitis flow.
Acceleration on KR260 with Vitis 24.2 (1)
387
Accelerate trigonometric calculations on hardware by using the classical CORDIC together with DMA
Using CORDIC and DMA on the Ultra96 board
525
Complete flow from scratch: Vivado platform, Petalinux build and hardware kernel build on Vitis, on the MYIR development board MYD-CZU4EV
Hardware acceleration in FPGA with Vivado and Vitis
1.1K
Empower your embedded system with a host USB 3.0 to interface a multitude of devices
Host USB 3.0 on the MYIR MYC-CZU3EG
536
A practical example on device tree configuration for specific hardware
Petalinux with Ethernet on the MYIR MYC-CZU3EG
1.4K
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