SGDH's Traffic Light Project

Introduction

In the SGDH's Verilog LRM lecture, we learned FSM and Counter.

By combining these two contents, we can create a traffic light project.We also learned synthesizable syntax, and we will prove that the Verilog code we designed will soon be made into HW.

To prove this, we uploaded the RTL code we designed onto the Zybo-Z7 20 board.

How to implement it on FPGA?

The time for each light to blink is as follows.

• RED 5 sec
• Yellow 1 sec
• Green 2 sec

When the switch is on, the following FSM operates, and when the switch is off, all the LEDs are turned off.

In order to upload it to the FPGA, I created a wrapper called sgdh_traffic_light_top_fpga.

This code contains a clock, a switch, and an LED.

Inside the sgdh_traffic_light_top_fpga code, there is sgdh_traffic_light_top that we verified.

It is a very simple operation, but we covered A to Z of how to define, design, and verify the specifications.

Ending.

I hope it will be of great help to you in studying Verilog.

If you are interested in our lecture, please refer to the following link.

https://github.com/semisgdh

We are an organization for semiconductor design lectures in Korea and are very interested in semiconductor design education.

Thank you!