GNU Radio Toolkit on AXU2CGB Zynq UltraScale+ board - Part3

This is a Step-by-Step Tutorial how to create a Hardware Accelerator Platform for AXU2CGA/B Zynq UltraScale+ FPGA development board made by Alinx, that can be used for runnung GNU Radio applications with accelerating functions under the Xilinx Vitis toolset.

Adding the gr-satellites developed by EA4GPZ and building your own OOT modules is also included in this set of Tutorials.

This is the Part-3/4: Create a Vitis Platform with DPU

Creating a Vitis Platform with previous created Vivado project and PetaLinux SDK.

If you are looking for other parts of this set of tutorials, you can go there directly:

• Part-1 - Create the Vivado Hardware Design
• Part-2 - Software - Build the PetaLinux and GNU Radio
• Part-3 - Create a Vitis Platform and Application with DPU
• Part-4 - Build the AI model in Colab and Vitis-AI

Prepare Files for Platform Packaging

1- Go to the previously created platform directory under your project main directory, or create it if doesn’t exist.

$ pwd
# /tools/workspace/axu2cgb

$ mkdir platform
$ ls
# hardware  platform  software

cd platform

2- Create some new directories for storing some previously created files.

mkdir -p pfm/boot
mkdir -p pfm/sd_dir

3- Copy the generated Linux software boot components from Part-2 to pfm/boot directory.

$ cp ../software/axu2cgb_2021_2-petalinux/images/linux/zynqmp_fsbl.elf pfm/boot/
$ cp ../software/axu2cgb_2021_2-petalinux/images/linux/pmufw.elf pfm/boot/
$ cp ../software/axu2cgb_2021_2-petalinux/images/linux/bl31.elf pfm/boot/
$ cp ../software/axu2cgb_2021_2-petalinux/images/linux/system.dtb pfm/boot/
$ cp ../software/axu2cgb_2021_2-petalinux/images/linux/u-boot-dtb.elf pfm/boot/u-boot.elf

$ ls pfm/boot/
bl31.elf  pmufw.elf  system.dtb  u-boot.elf  zynqmp_fsbl.elf

NOTE: The last file u-boot-dtb.elf is renamed to u-boot.elf. Please, don't use the original u-boot.elf, because, it doesn't contain device tree block.

4- Copy the boot.scr and system.dtb to pfm/sd_dir folder.

$ cp ../software/axu2cgb_2021_2-petalinux/images/linux/boot.scr pfm/sd_dir/
$ cp ../software/axu2cgb_2021_2-petalinux/images/linux/system.dtb pfm/sd_dir/

$ ls pfm/sd_dir/
boot.scr  system.dtb

5- Install sysroot into pfm folder.

Before installing sysroot, you must unset the system variable LD_LIBRARY_PATH

export LD_LIBRARY_PATH=

Now, you can install the sysroot from the previously generated sdk.sh script.

$ ../software/axu2cgb_2021_2-petalinux/images/linux/sdk.sh -d pfm
Y

NOTE: The -d option tells the sdk.sh script where to install the sysroot.

PetaLinux SDK installer version 2021.2
======================================
You are about to install the SDK to "/tools/workspace/axu2cgb/platform/pfm". Proceed [Y/n]? 
Extracting SDK.....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................done
Setting it up...done
SDK has been successfully set up and is ready to be used.
Each time you wish to use the SDK in a new shell session, you need to source the environment setup script e.g.
 $ . /tools/workspace/axu2cgb/platform/pfm/environment-setup-cortexa72-cortexa53-xilinx-linux

Create a Vitis Platform

Before starting the Vitis IDE program make sure you have set all the following paths and settings:

source /tools/Xilinx/Vitis/2021.2/settings64.sh

export OPENCV_INCLUDE=/usr/include/opencv4/
export OPENCV_LIB=/usr/lib/x86_64-linux-gnu/
export LD_LIBRARY_PATH=/usr/lib/x86_64-linux-gnu/

NOTE: Set the LD_LIBRARY_PATH variable back, because it was removed during sysroot installation.

1- Launch Vitis IDE in the current platform folder in background mode and set the same folder as a workspace directory.

vitis &

Create a new platform: File > New > Platform Project and name it axu2cgb_2021_2-platform. Click Next.

In the Hardware Specification, click Browse button and select the XSA file generated by the Vivado at the end of Part-1.

/tools/workspace/axu2cgb/hardware/axu2cgb_2021_2-vivado/design_1_wrapper.xsa

Under Operating system select linux, psu_cortexa53 and 64-bit.

Uncheck Boot Components. Click Finish.

Click the linux on psu_cortexa53 domain.

Browse to the locations and select the directory or file needed to complete the dialog box for the following:

• Bit File - click Generate BIF (at the end of Browse button
• Boot Components - browse to pfm/boot
• FAT32 Partition Directory - browse to pfm/sd_dir

Leave all other settings as they are.

NOTE: Leave Linux RootFS and Sysroot Directory blank for now.

Build the Platform

In the Explorer tab window right click on the created platform:

• axu2cgb_2021_2-platform and select Build Project. Wait for few seconds to finish.

Export the Platform

In the Explorer tab window right click on the created platform: axu2cgb_2021_2-platform and select Exportas Archive. Select your platform name and tick Include build folders. Wait for several minutes to finish.

You can use this exported zip file for creating new projects.

Install Vitis-AI

We create a new application that integrate a Xilinx Deep Learning Processor unit DPU as a kernel. There is a script already provided from Xilinx that create everything we needed.

For more details about the DPU, please take a look at the DPU-TRD GitHub repository and read the PG338 DPU IP Product Guide.

At first we need to add the Vitis-AI repository into the Vitis IDE.

Launch Vitis IDE if you have not already. We can reuse the workspace of the previously created platform.

Open menu Window > Preferences > Library Repository tab > Add

Set the following:

• Input ID: vitis-ai
• Name: Vitis AI
• Git URL:https://github.com/Xilinx/Vitis-AI.git
• Branch: v2.0 or master

Apply and Close

Download the Vitis-AI library:

• Open menu Xilinx > Libraries.
• Find the Vitis-AI entry we just added.
• Click the Download button on it.
• Wait until the download of the Vitis-AI repository completes (several minutes).
• Click OK.
• git commit ID for v2.0 is: d02dcb6041663dbc7ecbc0c6af9fafa087a789de
• git commit ID for master is currently: ba8905493876674716ab08ea4266962193df970b

Create a DPU Application Project

Create a new Vitis-AI design on our previously created axu2cg_2021_2-platform.

Go to menu File > New > Application Project > Next.

Select platform axu2cgb_2021_2-platform. Click Next.

Name the project dpu-test, click next.

Set Domain: linux on psu_cortexa53

• Set Sys_root path to sysroot installation path in previous step:

tools/workspace/axu2cgb/platform/pfm/sysroots/cortexa72-cortexa53-xilinx-linux

• Set the Root FS to rootfs.ext4.

/tools/workspace/axu2cgb/software/axu2cgb_2021_2-petalinux/images/linux/rootfs.ext4

• Set Kernel Image to Image.

/tools/workspace/axu2cgb/software/axu2cgb_2021_2-petalinux/images/linux/Image

The last two files are located in axu2cgb_2021_2-petalinux/images/linux folder created in Part-2.

Click Next and select:

• dsa > DPU Kernel (RTL Kernel)

And click Finish to generate the application.

Update Build Target:

• Double click the system project file dpu-test_system.sprj and
• Change Active Build Configuration to Hardware.

DPU settings for AXU2CGB

Because the FPGA device on the axu2cgb board does not have enough resources to build the DPU with default configuration, we need to:

• Integrate only one kernel (not 2 by default).
• Change the DPU processor selection.
• Disable some functionality.

Open the dpu_conf.vh file from the dpu-test_kernels/src/prj/Vitis directory.

• Change B4096 to B1152 (line #26)
• Change DRAM_DISABLE to DRAM_ENABLE (line #59)
• Change CHANNEL_AUGMENTATION_ENABLE to CHANNEL_AUGMENTATION_DISABLE (line #92)
• Change DWCV_ENABLE to DWCV_DISABLE (line #103)
• Change RELU_LEAKYRELU_RELU6 RELU_RELU6 (line #136)

Fill free to experiment with some more options enabled in case you have more powerful FPGA, but:

• make sure POOL_AVG is enabled, because our model needs it. (line 114)

Save the file and check everything again, because the kernel build process lasts very long.

//Setting the arch of DPU, For more details, Please read the PG338 


/*====== Architecture Options ======*/
// |------------------------------------------------------|
// | Support 8 DPU size
// | It relates to model. if change, must update model
// +------------------------------------------------------+
// | `define B512               
// +------------------------------------------------------+
// | `define B800                 
// +------------------------------------------------------+
// | `define B1024                 
// +------------------------------------------------------+
// | `define B1152                 
// +------------------------------------------------------+
// | `define B1600                 
// +------------------------------------------------------+
// | `define B2304                 
// +------------------------------------------------------+
// | `define B3136                 
// +------------------------------------------------------+
// | `define B4096                 
// |------------------------------------------------------|

`define B1152 

// |------------------------------------------------------|
// | If the FPGA has Uram. You can define URAM_EN parameter               
// | if change, Don't need update model
// +------------------------------------------------------+
// | for zcu104 : `define URAM_ENABLE               
// +------------------------------------------------------+
// | for zcu102 : `define URAM_DISABLE                 
// |------------------------------------------------------|

`define URAM_DISABLE 

//config URAM
`ifdef URAM_ENABLE
    `define def_UBANK_IMG_N          5
    `define def_UBANK_WGT_N          17
    `define def_UBANK_BIAS           1
`elsif URAM_DISABLE
    `define def_UBANK_IMG_N          0
    `define def_UBANK_WGT_N          0
    `define def_UBANK_BIAS           0
`endif

// |------------------------------------------------------|
// | You can use DRAM if FPGA has extra LUTs               
// | if change, Don't need update model
// +------------------------------------------------------+
// | Enable DRAM  : `define DRAM_ENABLE               
// +------------------------------------------------------+
// | Disable DRAM : `define DRAM_DISABLE                 
// |------------------------------------------------------|

`define DRAM_ENABLE 

//config DRAM
`ifdef DRAM_ENABLE
    `define def_DBANK_IMG_N          1 
    `define def_DBANK_WGT_N          1
    `define def_DBANK_BIAS           1
`elsif DRAM_DISABLE
    `define def_DBANK_IMG_N          0
    `define def_DBANK_WGT_N          0
    `define def_DBANK_BIAS           0
`endif

// |------------------------------------------------------|
// | RAM Usage Configuration              
// | It relates to model. if change, must update model
// +------------------------------------------------------+
// | RAM Usage High : `define RAM_USAGE_HIGH               
// +------------------------------------------------------+
// | RAM Usage Low  : `define RAM_USAGE_LOW                 
// |------------------------------------------------------|

`define RAM_USAGE_LOW

// |------------------------------------------------------|
// | Channel Augmentation Configuration
// | It relates to model. if change, must update model
// +------------------------------------------------------+
// | Enable  : `define CHANNEL_AUGMENTATION_ENABLE              
// +------------------------------------------------------+
// | Disable : `define CHANNEL_AUGMENTATION_DISABLE                
// |------------------------------------------------------|

`define CHANNEL_AUGMENTATION_DISABLE

// |------------------------------------------------------|
// | DepthWiseConv Configuration
// | It relates to model. if change, must update model
// +------------------------------------------------------+
// | Enable  : `define DWCV_ENABLE              
// +------------------------------------------------------+
// | Disable : `define DWCV_DISABLE               
// |------------------------------------------------------|

`define DWCV_DISABLE

// |------------------------------------------------------|
// | Pool Average Configuration
// | It relates to model. if change, must update model
// +------------------------------------------------------+
// | Enable  : `define POOL_AVG_ENABLE              
// +------------------------------------------------------+
// | Disable : `define POOL_AVG_DISABLE                
// |------------------------------------------------------|

`define POOL_AVG_ENABLE

// |------------------------------------------------------|
// | support multiplication of two feature maps
// | It relates to model. if change, must update model
// +------------------------------------------------------+
// | Enable  : `define ELEW_MULT_ENABLE           
// +------------------------------------------------------+
// | Disable : `define ELEW_MULT_DISABLE               
// |------------------------------------------------------|

`define ELEW_MULT_DISABLE

// +------------------------------------------------------+
// | RELU Type Configuration
// | It relates to model. if change, must update model
// +------------------------------------------------------+
// | `define RELU_RELU6
// +------------------------------------------------------+
// | `define RELU_LEAKYRELU_RELU6
// |------------------------------------------------------|

`define RELU_RELU6

// |------------------------------------------------------|
// | DSP48 Usage Configuration  
// | Use dsp replace of lut in conv operate 
// | if change, Don't need update model
// +------------------------------------------------------+
// | `define DSP48_USAGE_HIGH              
// +------------------------------------------------------+
// | `define DSP48_USAGE_LOW                
// |------------------------------------------------------|

`define DSP48_USAGE_HIGH 

// |------------------------------------------------------|
// | Power Configuration
// | if change, Don't need update model
// +------------------------------------------------------+
// | `define LOWPOWER_ENABLE              
// +------------------------------------------------------+
// | `define LOWPOWER_DISABLE               
// |------------------------------------------------------|

`define LOWPOWER_DISABLE

// |------------------------------------------------------|
// | DEVICE Configuration
// | if change, Don't need update model
// +------------------------------------------------------+
// | `define MPSOC              
// +------------------------------------------------------+
// | `define ZYNQ7000               
// |------------------------------------------------------|

`define MPSOC

Remove the SoftMax function and one kernel instance

We use software implementation of the SoftMax function that run on the main CPU, so we remove it from the kernel to save some resources.

Also we can only integrate only one kernel instance of the DPU, if we are using AXU2CGB board.

Double click dpu-test_system_hw_link.prj:

• Remove sfm_xrt_top function by right clicking and select Remove.
• Change the Compute Units of DPUCZDX8G to to 1.

V++ Configuration settings

In case we removed one kernel instance of the DPUCZDX8G, we also need to remove all clocks and connectivity dedicated to the previously removed second instance.

• Go to Assistant View.
• Double click dpu-test_system [System].
• Expand the left tree panel and find dpu-test_system > dpu-test_system_hw_link > Hardware > dpu.

Click the ... button in the line named V++ configuration settings. Change the V++ linker settings window content to the following:

[clock]
freqHz=300000000:DPUCZDX8G_1.aclk
freqHz=600000000:DPUCZDX8G_1.ap_clk_2

[connectivity]
sp=DPUCZDX8G_1.M_AXI_GP0:HPC0
sp=DPUCZDX8G_1.M_AXI_HP0:HP0
sp=DPUCZDX8G_1.M_AXI_HP2:HP1

Click OK, Apply, Apply and then Apply and Close.

Adding a custom Python Application to project (optional)

Now, we add our new python test scripts from the GitHub repository from the command line interface.

• Go to Ubuntu Terminal program and change the directory to dpu-test/src.
• Clone the repository named test-dpu from my (S59MZ) GitHub account.

$ cd platform/dpu-test/src

$ git clone https://github.com/s59mz/test-dpu
$ cd test-dpu
$ git checkout main
$ rm -rf test-dpu/.git
$ cd ../../..

Now we have a new directory test-dpu with some test python scripts.

NOTE: In case you have a different hardware than AXU2CGB board, that use SD0 interface for SD card (zcu102 or zcu104 board for example), you should checkout mmcblk0 branch instead of main.

Replace the old resnet50 model (optional)

You can replace the resnet50.xmodel in the app/model directory with a new re-compiled one, because we changed the DPU settings in the dpu_conf.vh file.

But only, if you want to run some DPU tests with the default included resnet50 model. Not needed for GNU Radio.

There is the re-built resnet50.xmodel already in the previously cloned GitHub repository in the dpu-test/models directory. Replace the old model with the re-built one.

$ cd dpu-test/src/app/model
$ rm resnet50.xmodel
$ mv ../../test-dpu/models/resnet50.xmodel .

NOTE: There is also the dpu_conf.vh file that should go to the dpu-test_kernels/src/prj/Vitis directory, in case you didn’t set the DPU configuration in the previous section already. You can compare both files, should be the same.

Packaging

Update the Packaging options to add app and this new test-dpu directory also on SD Card.

• Double click dpu-test_system.sprj
• Click... button on Package options
• Input:

--package.sd_dir=../../dpu-test/src/test-dpu --package.sd_dir=../../dpu-test/src/app

Click OK

NOTE: there is a space between /test-dpu and --package.sd_dir

NOTE: A new directory name to be added in the src directory should not start with the word dpu-something. That causes a Makefile error.

Build the Application

Right Click on the dpu-test_system[axu2cgb_2021_2-platform] system project and select Build Project. Wait for about an hour to finish.

The generated SD card image is located at dpu-test_system/Hardware/package/sd_card.img. We need that one for our Target board.

The most important file, generated in this build process, is dpu.xclbin. It is the FPGA binary image that implements the DPU kernel in the FPGA. It is located in Hardware directory, added to the boot partition of the SD card and included in the sd_card.img image.

Test the GNU Radio Platform on Target

Prepare the empty SD card, size at least 8GB.

The prepared SD card image for AXU2CGB board can also be downloaded from the GitHub repository.

Write the sd_card.img created in the previous step on an empty SD card with a Linux DD command or similar program for writing SD card images (Etcher).

NOTE: Double check the output device of=/dev/sd... It must point to the SD card, unless you can loose all data on your Host machine.

$ cd axu2cgb/platform/dpu-test_system/Hardware/package
$ sudo dd if=sd_card.img of=/dev/sd?? bs=512; sync

Insert the SD Card into the AXU2CGB board, connect the Serial Console to your Host machine via USB cable and run the Serial Terminal program, minicom for example.

$ minicom -D /dev/ttyUSB0 -b 115200

Connect the Ethernet cable to the board. The board and the Host Machine should be in the same local area network.

Power up the AXU2CGB board. The U-Boot should start, then the Linux Kernel and the rootfs file system. Wait for a prompt.

Check the Linux version and the IP address of the board by running the "uname -a" and ifconfig Linux commands, respectively.

$ uname -a
$ ifconfig

Note the IP address, because we need it for SSH -X access.

Prepare the Host Machine

Now we use a Host computer as a Display, so we prepare the Host computer as X11 Server and ssh to the board with "-X" option.

On the Host computer:

• Check the $DISPLAY variable. Should be ":1".
• Add the local connection to the access control list. Type: "xhost +local:"
• Open ssh -X session to the board from the Host machine.
• Login as root with the password root.

$ echo $DISPLAY
$ xhost +local:
$ ssh -X root@192.168.1.73

Prepare the Target

The first thing to do is resize the EXT4 partition of the SD Card. This command should be run only once.

resize-part /dev/mmcblk1p2

Also, update the Packet Manager.

$ dnf update

NOTE: If you want to build your own OOT modules for GNU Radio, the following python libraries should be installed manually:

$ pip3 install Click
$ pip3 install click-plugins

NOTE: For decoding signals from satellites by using the gr-satellites module from EA4GPZ, install the following two additional libraries:

$ pip3 install construct
$ pip3 install requests

Testing the DPU unit on real Target

Now, we can run some tests on the board.

Before running any tests, you should set some system variables.

For using the DPU unit, this variable points to the FPGA binary image:

$ export XLNX_VART_FIRMWARE=/media/sd-mmcblk1p1/dpu.xclbin

For executing any C/C++ programs that uses DPU, this variable points to the needed libraries:

$ export LD_LIBRARY_PATH=/media/sd-mmcblk1p1/app/samples/lib

For using any GNU Radio modules, this variable points to the location of Python packages:

$ export PYTHONPATH=/usr/lib/python3/dist-packages/

To get the DPU fingerprint, needed for building your own AI models, the "xdputil query" command can be used:

$ export XLNX_VART_FIRMWARE=/media/sd-mmcblk1p1/dpu.xclbin
$ xdputil query

Find the "fingerprint":"0x100002062010103" parameter at the near end of the console print and store this parameter inside curled brackets {} to a new created arch.json file.

Store this file on the Host machine somewhere. This file is needed for compiling AI models with Vitis-AI.

$ echo '{"fingerprint":"0x100002062010103"}' > arch.json

NOTE: Make sure that brackets and double quotes are included in the file.

$ cat arch.json
{"fingerprint":"0x100002062010103"}

NOTE: The original arch.json file generated by Vitis-AI during creating dpu-test application has wrong value, due to unknown reason. The fingerprint value ended with -203 instead of -103. Please, use the fingerprint value read from FPGA directly for compiling your own models.

Change directory to the test-dpu on BOOT partition of the SD card, where all needed testing scripts are located:

$ cd /media/sd-mmcblk1p1/test-dpu

There are five bash test scripts lotated in this directory, all started with "run_" prefix.

Feel free to explore the scripts and check, if all system variables in the scripts points to the right location, especially check mmcblk1p1 or mmcblk0p1 SD card partitions, depending on your hardware platform you chose.

$ ls -l run_*

run_recognize_image.sh
run_test_performance.sh
run_test_accuracy.sh

run_gnuradio.sh
run_rf_classification.sh

Run each script and check if everything works correctly.

The last two tests that uses GNU Radio should be run via ssh -X session, because they use a graphic display through X11 Server on your host machine.

NOTE: In case of repeating errors, try to reboot the board first.

$ reboot -h

Image Classification Test

This is the original DPU test included in the AMD-Xilinx tutorial. The test recognize an object in a provided image.

Run the run_recognize_image.sh script:

$ pwd
/media/sd-mmcblk1p1/test-dpu

$ ./run_recognize_image.sh

Recognising Unknown Image...
score[688]  =  0.999914     text: oscilloscope, scope, cathode-ray oscilloscope, CRO,
score[662]  =  1.30062e-05  text: modem,
score[844]  =  1.30062e-05  text: switch, electric switch, electrical switch,
score[592]  =  1.01292e-05  text: hard disc, hard disk, fixed disk,
score[811]  =  7.88864e-06  text: space heater,
/media/sd-mmcblk1p1/test-dpu

The test is passed if the picture is recognized correctly (oscilloscope in this case). Feel free to change the picture inside the script with a different one.

RF Modulation Classification Performance Test

This test measures the maximum possible frame rate of inference.

Run the run_test_performance.sh script.

Make sure the measured FPS is about 500 frame per seconds for AXU2CGB board.

$ pwd
/media/sd-mmcblk1p1/test-dpu

$ ./run_test_performance.sh

Number of RF Samples is  2000
FPS=532.79, total RF frames = 2000.00 , time=3.753795 seconds

RF Modulation Classification Accuracy Test

This test measures the accuracy of the model with a given test dataset.

Run the run_test_accuracy.sh script.

Make sure the top-1 accuracy is about 0.53. We used a baseline model that was trained with only 6% of available datasets samples.

$ pwd
/media/sd-mmcblk1p1/test-dpu

$ ./run_test_accuracy.sh

Number of RF Samples Tested is  998
Batch Size is  1
Top1 accuracy =  0.53

FM Radio Test

It is a simple FM radio implemented in the GNU Radio platform. The board should have inserted an RTL-SDR USB dongle into one of the available USB ports on the AXU2CGB board.

The RTL-SDR USB dongle is a software defined radio receiver. An appropriate small antenna should be connected to the RTL-SDR.

This test uses a graphic display and should be run through ssh -X session.

Connect a USB Sound Card with speakers or phones connected to the audio jack input of the sound card. It is also possible to route audio to X11 server, without using any USB sound cards.

When everything is connected, run the run_gnuradio.sh script.

• The GNU Radio will start.
• Click on the Play button on the Toolbox above or press F6 on the keyboard.
• A new GUI would open. Ignore the Warning message (it shows only once).
• Resize the new GUI to be more visible.
• Set the Frequency in the GUI to any local FM broadcast radio station nearby.
• You should hear the selected local radio station in the speakers (if they are connected) and see the received radio spectrum in the GUI widget.

To route audio into X11 Server, close the radio GUI and double click on the Audio Sink block:

• Delete the content of the Device Name field that has a value of "hw:0, 0".
• Click OK and then Play again.
• You should hear the audio on your Host computer's speakers now.

Feel free to change the frequency to any other FM broadcast stations nearby.

Running the RF Modulation Classification test on GNU Radio

This test run a simple GUI application developed on GNU Radio platform that runs under Python.

The application receives signals on an radio amateur 2m band and predicts modulations of the receiving digital signals in real time. For inference it uses the Deep learning Processor Unit (DPU) implemented in the FPGA on the board.

The test uses a graphic display and should be run through the ssh -X session.

The board should have inserted an RTL-SDR USB dongle into one of the available USB ports on the AXU2CGB board.

It is a software defined radio receiver as a USB dongle. An external VHF/UHF antenna is recommended be connected to the RTL-SDR.

Connect a USB Sound Card with speakers or phones connected to the audio jack input of the sound card. It is also possible to route audio to X11 server, without USB sound card.

NOTE: The tablet computer works as X11 Server only and shows the GUI from GNU Radio, running on the FPGA board.

When everything is connected, run the run_rf_classification.sh script.

• The application starts automatically. Resize the GUI appropriately.
• The SDR receiver is tuned to 144.8 MHz on radio amateur band and listens for some random digital signals on this band.
• When a strong signal appears, it can be shown on a waterfall.
• At this moment the program start predicting the modulation on the received signal. The predicted modulation is printed on the SSH console and the histogram counts all of the predicted class indexes.
• Samples of analyzed signal are also shown in time domain (oscilloscope).

The AI model is already included in the application in the test-dpu/models/rfClassification.xmodel file. It is a baseline model trained with 10 epochs only and with only 6% of the available samples from the dataset.

Next Step

Feel free to build your own model and train it with more samples in the next / last tutorial of these series:

Part-4 - Build the AI model in Colab and Vitis-AI