Published August 3, 2023 © MIT

6502 SBC prototype - testing PCB rev 1.0

How do you test and fix your first PCB rev? What did I learn from the experience of moving perfboard prototype to a PCB?

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6502 SBC prototype - testing PCB rev 1.0

Things used in this project

Hardware components

65C02

MC6850

65C22 VIA

PCBWay Custom PCB

Software apps and online services

Arduino IDE

PuTTY console

PrusaSlicer

Autodesk Fusion

VASM

Hand tools and fabrication machines

SDS1104X-E (100 MHz) Oscilloscope

Story

The Build

This isn't a project in the conventional sense. I'm sharing my build process which includes mistakes, techniques and tips for taking on something like this.

While this is not the first time I've ordered a PCB online, it is the most complicated one I've done and I really didn't expect revision 1 to work at all.

Perfboard Version

What is it? This is a variant of Ben Eater's breadboard computer that he walks through in a series of highly motivating videos. I include a 65C22 VIA (supporting both the Hitachi flavour LCD and the PS/2 keyboard) and a serial interface.

Schematic for reference (PDF in attachments)

How does my design differ from a regular BE6502?

I do address decoding using a ATF 22V10C CPLD : less chips, more flexibility
thanks to the CPLD, map IO to the high end of the 65C02 zero page
my serial interface uses the Motorola 6850 ACIA (the tx bug of the 6551 ACIA and associated delay hack is not ideal)
Garth Wilson's reset circuit (rather than Ben's)
I'm running at 4 mHz, not 1 mHz
other minor mods like the 3.3k pullup on IRQ (not sure if 65C02 has internal -advice from forums)
10k pullup on RX and TX on the RS232 DB9 side (advice from forums)
used the 'spare' pin on the VIA for a built-in LED (made the LCD firmware more complicated because it maintains the state of the LED)
I assume WDC 65C02S instructions in all my firmware (since my ports are on the zero page, this means I can use bit instructions like BBRn, BBSn, RMBn and SMBn on them directly without needing to go via a register).

I'd been working on the perfboard version for a while and it was time to move at least 4 of those boards to a single PCB: CPU, RAM, EEPROM and VIA.

Yay! Beautiful fresh boards.

Super excited when the board arrived in the mail only to be immediately disappointed with myself for not being more thorough about reviewing all the footprints : my ceramic capacitors were all using what looks like either very small leads or some sort of surface mount version or just a mistake.

Sweating decoupling capacitors surface mount style.

Decoupling capacitors should not be the hardest part of the build.

I live in a small town in New Zealand : we don't have a lot of variety when it comes to buying components locally. Everything takes more than a day to get here. So, I should have looked more closely at the footprint for the fuse holder. When someone says they "used a paperclip for the fuse", this is not usually what they mean.

Paperclip as fuse holder adapter / jig

Incremental Build

I started from the position of there must be something wrong with my board so how do I build it in a way that the mistake or mistakes don't just become an unsolvable mystery? My approach is to build incrementally and test every system as I go. Start with the simplest subsystem, build it, test it and then move on to the next system.

The alternative to an incremental build would be to just assemble the whole thing, turn the power on and hope for the best. With this approach it would be harder to figure out the reason for failure if it didn't just work the first time. For a proven design, this approach is fine. For something that's barely in the prototype stage, this is a recipe for failure.

So, incremental build and test-as-we-go:

Step 1 - Minimal Power Circuitry

Power Circuitry

Start with just enough to light the power LED and then move on to the power up reset circuitry.

Inspecting the timing of the reset circuitry

Step 2 - CPU

To start, I added the oscillator can and tested it using the oscilloscope. Then I built the usual NOP tester using resistors to spell out 0xEA (6502 for NOP) on the data bus and watched the high address lines using the oscilloscope.

Adding an oscillator and CPU

Address lines counting neatly in binary for the NOP test

Step 3 - ROM

Same test, only replacing the resistors with an EEPROM and including a small program (so I have to watch the lower address lines instead). I also needed address decoding to select the ROM so programmed and installed my CPLD for this.

This time I also switched to my slow Ben Eater style clock for testing so that I could watch the blinky LEDs on the address bus to see the binary counting through addresses for the NOP test.

Added EEPROM and CPLD address decoder

Satisfying blinky lights counting in binary on the address bus through NOP test program

Step 4 - RAM

The easiest way to test RAM is to try to run a small program that relies on the stack: something that makes a subroutine call and returns. For this test I also use my Arduino Mega probe / debugger and again run on the slow clock so the Arduino can keep up.

Added RAM and using Arduino Mega debugger probe

Arduino probe says I'm writing to the stack (in RAM) and making it back from a subroutine call

Step 5 - IO

So far, so good. Time to add the VIA and start testing peripherals. The first and easiest IO thing to test is the built-in LED that I put on the one unused pin of port A of the VIA. A simple program with a delay between turning the LED on and off and, sure enough, blinking LED.

Classic blink : we've arrived!

And then things went sideways: as soon as I plugged in and tried to get the LCD working, the wheels fell off. Surprisingly, the machine kept working despite my blunder. Using the oscilloscope again I probed the various outputs from the VIA and noticed something odd about one of the control lines for the LCD, the RW line: it wasn't sitting at nice clean 0V or 5V. It was at some dirty middle ground when I accessed the VIA. Why?

Why do those two signals look so similar to each other?

This time discovering the actual issue was down to pure dumb luck : I happened to be probing the control line on the LCD at the same time I had a probe on the R/W line of the CPU and they looked very very similar (when not using the VIA).

The error I made in the PCB software was to treat the NET nodes on the edge connector of the LCD the same as those on the CPU. Well, not something I consciously did. Just something that happened. So the LCDs RW control line got connected via the PCB to the CPU RW line even though the two are completely unrelated in the real world : they had the same name.

Time for some PCB surgery.

2 cuts to disconnect the LCD's RW line from the CPUs RW control line.

Reconnecting the LCD's RW to the VIA port

LCD working, first PCB repair a success

Step 6 - more IO

Testing the PS/2 keyboard interface with the same VIA was a bit more dramatic: the moment I powered up with the keyboard plugged in, the fuse blew. Turns out the footprint I had used for the PS/2 connector on the PCB had all its pins inverted! (solder side view rather than component side view). Check the obscure / less popular footprints!!

Also, always include a fuse in the power circuit.

Since these sockets are hard to source, I had also included a set of header pin holes as an alternative for the PS/2 keyboard. I changed the fuse, switched to the header pins and instant success with the next peripheral.

Screwdriver as weight for camera pose : essential equipment

Step 7 - first daughter board

At the time I designed the main board I was still struggling to make the 6551 ACIA work reliably as my serial interface so I opted not to include it in the main board for now. Later I had great success with the Motorola 6850 so I rush ordered a board for that design from PCBWay. I'm heading off on a trip soon so I was under a bit of a deadline and didn't really expect the boards to get here on time.

One of the things I really like about PCBWay is the amount of detail in tracking progress for both the production phase and the shipping phase, all on their website (rather than that of the shipping company).

Note: PCBWay has offered to sponsor the next revision of my main board so I'm probably a little biased about them now but so far it has all been on my own dollar. I'd use them whether they pay for my boards in future or not. They're great.

Production Tracking

Shipping Tracking - easy to hit the <F5> key ..

Opening one of these little boxes always feels exciting to me

Back to the build: again, those damn capacitor footprints. This time I just mounted the MAX232 charge pump capacitors directly on the MAX232 itself - much more reliable than wobbly "surface mount" ceramics (ok if a decoupling capacitor fails because it wobbles, not ok if a charge pump capacitor fails).

Notice all the empty footprints? C2..C5 are now mounted ON the MAX232 chip.

More isolated testing : this time I test the MAX232 part of the circuit before completing the rest of the board by plugging it into the serial port of my laptop and confirming that I'm getting clean TTL characters out. It made sense to check based on my unconventional mounting of the capacitors:

had I shorted to the ground plane anywhere?
had I overheated the chip by soldering directly to its pins?

Oscilloscope shows a healthy signal of serial bits.

FYI: This oscilloscope can decode serial signals so I can actually see which characters I'm pressing on the keyboard in the serial terminal.

Testing the MAX232

I complete the board, plug it in and... nothing. One more bizarre failure : probing with the scope showed me I had no serial clock signal and it appears I had a faulty can oscillator.

Replaced the can oscillator with a good one and success. Always good to have spares of crucial components on hand.

Yeah, that's not a square wave

Different can oscillator and a complete working serial board

I use WozMon as my default test application for the serial interface. Something cool about getting the same code running as Steve Wozniak did back in 1977.

WozMon via the ACIA 6850 board at 57600 baud

Summary of Blunders - What did I learn?

Examine your footprints in your PCB design : using the wrong footprint for all my ceramic capacitors was the worst mistake and made assembly so much harder than it should have been.
Check your NET names: just because a pin is named RW, doesn't mean it should be connected to the CPU's RW. ;-)
Examine obscure footprints very closely. The PS/2 keyboard connector footprint had its pins reversed (component side rather than board side). Plugging in a keyboard dead shorts the power rails (always use fuses on the supply). The fuse holder footprint didn't match anything I could source locally.
Increase the clearance between PCB traces: if you know you are going to need to modify your board, make it easier to cut and connect traces by giving yourself more wiggle room.
Only put the ground plane on the component side. If you leave the solder side cleaner it makes it easier to modify without shorting to ground.
Take more time to label everything in the silk screen: I was in a hurry so, although each component is labelled and numbered, they don't all include part names. For many, the part name is obscured once the part is placed. My expansion bus connector could really use some labels. My expansion bus connector is actually in the reverse direction of what I intended: I wanted the daughter cards to face the front. If I had labelled it, I would have noticed this and flipped it around.
Use bigger footprints for connectors and switches and label them all thoroughly.
Put more thought into the position of the EEPROM with larger ZIF sockets in mind. Make it easier for fat fingers.
Sometimes you are just unlucky and a component is faulty : test them before placing them where possible:
- AVO meter: resistors, capacitors, diodes
- Oscilloscope: can oscillators
- TL 866 EEPROM programmer: tests TTL chips
And, when the component only costs a few bucks, get some spares.

Improvements for the Next Version

Include the serial interface on the main board.
Add another button hooked up to NMI as a 'break'.
Built-in slow clock and single step with switches and LED indicators.
Built-in edge connector for my Arduino Mega probe / debugger just to make it easier to connect / disconnect.
The oscillator can footprint for the main board assumed my can would be DIP-8. I should always accommodate both variants: DIP-8 and DIP-14. This applies to the oscillator can on the 6850 daughterboard too. With more options possible then I can:
- use a 1 mHz full can rather than a 4 mHz half can on the main board
- use a 1.8432 mHz full can rather than a 3.6864 mHz on the 6850 board
(giving me a minimum baud of 28800 rather than 57600)

What's Next?

Circling back to the point of this whole exercise : getting Hopper running on a vintage machine. Now that I have some decent reliable hardware, I'll be focusing on the software side for a while.

Code

; 65C22 VIA
PORTB = $F0
PORTA = $F1
DDRB  = $F2
DDRA  = $F3

  .org $8000  ; physical ROM starts at $8000
  .org $A000  ; addressable ROM starts at $A000

; Tests the VIA (built-in LED)
; - does not use RAM
; - does not use Timer
; - obviously requires RAM
;
; 1 mHz clock: A = 2 should give ~600ms delay
; 4 mHz clock: A = 6 should give ~500ms delay
;
testLEDOnly:
  lda #%11111111
  sta DDRA ; LCD: set all pins on port A to output


fastLoop: ; for slow clock
  smb7 PORTA ; turn the built-in LED on
  lda #%00000000
  rmb7 PORTA ; turn the built-in LED off
  bra fastLoop

nextLoop:
  smb7 PORTA ; turn the built-in LED on
  
  lda  #6     ; inner loop is ~330,000 cycles so this would be A x 330,000
  ldy  #255   ; (2 cycles)
  ldx  #255   ; (2 cycles)
delayLoopOn:
  dex          ; (2 cycles)
  bne  delayLoopOn   ; (3 cycles in loop, 2 cycles at end)
  dey          ; (2 cycles)
  bne  delayLoopOn   ; (3 cycles in loop, 2 cycles at end) 
  dec
  bne  delayLoopOn   ; (3 cycles in loop, 2 cycles at end) 
  
  rmb7 PORTA ; turn the built-in LED off
  
  lda  #6     ; inner loop is ~330,000 cycles so this would be A x 330,000
  ldy  #255   ; (2 cycles)
  ldx  #255   ; (2 cycles)
delayLoopOff:
  dex          ; (2 cycles)
  bne  delayLoopOff   ; (3 cycles in loop, 2 cycles at end)
  dey          ; (2 cycles)
  bne  delayLoopOff   ; (3 cycles in loop, 2 cycles at end) 
  dec
  bne  delayLoopOff   ; (3 cycles in loop, 2 cycles at end) 

  bra nextLoop

irq:
  rti

nmi:
  rti


; Reset/IRQ vectors
  .org $fffa
  .word nmi
  .word testLEDOnly
  .word irq
  
  
; http://forum.6502.org/viewtopic.php?p=62581#p62581
  ; delay 9*(256*A+Y)+8 cycles
  ; assumes that the BCS does not cross a page boundary
  ; A and Y are the high and low bytes (respectively) of a 16-bit value; multiply that 16-bit value by 9, then add 8 and you get the cycle count
  ;
  ; Note: I didn't bother counting the jsr and rts in the delay time for now.
  ;
  ;            1Mhz Clock     800Hz Clock
  ;            A      Y       A     Y
  ; 500ms      217    43      0     43
  ;  50ms      21    178      0     4
  ; 4.5ms       1    243      0     0
  ; 150us       0     16      0     0
  ;  
  ;  delayLoop:
  ;  cpy #1        ; 2
  ;  dey           ; 2
  ;  sbc #0        ; 2
  ;  bcs delayLoop ; 3

Credits

Michael Cartwright

21 projects • 16 followers

Contact

Thanks to Ben Eater.

Comments

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6502 SBC prototype - testing PCB rev 1.0

Things used in this project

Hardware components

Software apps and online services

Hand tools and fabrication machines

Story

The Build

Incremental Build

Step 1 - Minimal Power Circuitry

Step 2 - CPU

Step 3 - ROM

Step 4 - RAM

Step 5 - IO

Step 6 - more IO

Step 7 - first daughter board

Summary of Blunders - What did I learn?

Improvements for the Next Version

What's Next?

Schematics

6502 Main Board - Rev 1.0

Code

65C02 Blink

NOPs in a loop

RAM test using subroutine call

Credits

Michael Cartwright

Comments

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6502 SBC prototype - testing PCB rev 1.0

6502 SBC prototype - testing PCB rev 1.0

Things used in this project

Hardware components

Software apps and online services

Hand tools and fabrication machines

Story

The Build

Incremental Build

Step 1 - Minimal Power Circuitry

Step 2 - CPU

Step 3 - ROM

Step 4 - RAM

Step 5 - IO

Step 6 - more IO

Step 7 - first daughter board

Summary of Blunders - What did I learn?

Improvements for the Next Version

What's Next?

Schematics

6502 Main Board - Rev 1.0

Code

65C02 Blink

NOPs in a loop

RAM test using subroutine call

Credits

Michael Cartwright

Comments

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