PyFive

PyFive

The PyFive project was originally conceived as a libre silicon MCU capable of easily running Micropython/CircuitPython. It would host a VexRiscv processor and have a USB interface along with other standard peripheral interfaces. Stretch goals included having an FPGA interface and/or software defined peripherals.

In 2019, Google sponsored a free ASIC multi-project wafer (MPW) shuttle program in collaboration with eFabless and the SkyWater foundry. Not only did they provide an unprecedented open source PDK for the 130nm process node but also allowed teams to submit open source ASIC designs to a series of shuttles free of charge. The chip designs from up to 40 teams are added to an MPW and submitted for a fabrication shuttle on a regular cadence.

First Google-Sponsored MPW Shuttle Launched at SkyWater

The PyFive ASIC was one of the 40 designs selected to be included on MPW-1. The first PyFive design was intended to be a test of the ASIC implementation of the no2usb USB core by Sylvain Munat (tnt). The USB core was hardened along with some UART, video and PDM IP to fill in more of the available area on the chip design.

While waiting for the first batch of chips to be delivered, the PyFive team further developed the IP and a firmware implementation of CircuitPython on a special ECP5 FPGA board designed by Greg Davill.

Unfortunately, the MPW-1 had some hold time violations rendering the ASICs "dead on arrival" when delivered. The PyFive team in a ditch effort created a post mortem carrier design which allowed some signs of life to be extracted from the MPW-1 chips.

YouTube Video of tnt Bringing Pyfive MPW-1 Back to Life

The team is currently funding as the first GroupFund on GroupGets.

Crowd funding initiative on GroupGets

Funding will help support the development of the various IP components.

IP Blocks

Taped out and partially tested

• UART
• PDM
• Simple video output

Planned contributions

• USB
• Various RAM configurations (main RAM, caches, etc)
• PSRAM interface
• HyperRAM interface
• Flash interface
• ROM core generator
• Software defined peripheral block

The PyFive team will also continue to provide PCB design support, testing support and feedback for the Caravel project as a whole

Advisors

Sean Cross (xobs)

Scott Shawcraft (tannewt)

Matt Venn (mattvenn)

Tim Ansell (mithro)

Charles Papon (Dolu)