A High-Speed ADC Microchip

Researchers from Brigham Young University have designed a power-efficient, high-speed analog-to-digital converter that consumes only 21 milli-Watts of power at 10GHz for ultra-wideband wireless communication applications. ADCs can be found in almost every electronic device that converts an analog signal into digital, including microphones, smartphones, and flat panel displays. The problem with creating ADCs with high-speed bandwidth is the amount of power they consume at faster speeds. To solve that problem, the team focused on a key component: the DAC (digital-to-analog) converter.

The researchers were able to gain those high speeds by reducing the loading from the DAC by scaling the capacitor parallel plate and spacing. They also grouped unit capacitors differently over the conventional method, which are part of the same bit in the DAC rather than interleaved throughout. This allowed them to lower the bottom-plate parasitic capacitance three-fold, lowering power consumption while boosting speed.

They then incorporated a bootstrap switch with dual pathways that can be independently optimized, which also increases speed but doesn't rely on additional hardware because it splits exiting devices, making route changes in the circuits. "We've proven the technology of the chip here at BYU and there is no question about the efficacy of this particular technique," states BYU professor Wood Chiang. "This work really pushes the envelope of what's possible and will result in a lot of conveniences for consumers. Your Wi-Fi will continue to get better because of this technology, you'll have faster upload and download speeds, and you can watch 4K or even 8K with little to no lag while maintaining battery life."

According to Chiang, other ADC applications include autonomous vehicles, wearables, smart contact lenses, and implantable devices.