Acceleration Robotics Partners with PlanV for a Robotics-Specific Open Source RISC-V Microcontroller
Designed specifically for ROS 2, the roscore-v RISC-V microcontroller promises reduced latencies and new real-time capabilities.
Performance-boosting specialist Acceleration Robotics has announced a partnership with Germany's PlanV, which will see the pair building a microcontroller specifically for Robot Operating System (ROS) 2 robotics projects, using the free and open source RISC-V architecture as the basis.
"Though microcontrollers are generally accepted as programmable specialized devices, most MCUs [Microcontroller Units] used in robotics today have general purpose building blocks," explains Acceleration Robotics founder Víctor Mayoral-Vilches of the problem the companies are looking to solve. "There is not much robotics-specific in any of them."
"Most roboticists today use ROS 2," Mayoral-Vilches continues, "and the avenues to enable this in microcontrollers are often complex and hard to optimize for latency and real-time. Our goal is to design an open source and hardware MCU that has built-in robotics capabilities and we will do so by building upon open standards like ROS 2 and RISC-V."
"The single most interesting feature of the RISC-V ISA and related open source implementations is the possibility of building extensions and customizations," adds PlanV founder Massimiliano Giacometti of the decision to build around RISC-V. "The growing field of hardware accelerated robotics is the perfect playground where to experiment and demonstrate the capabilities, flexibility and maturity of these technologies."
The partnership marks the first time Acceleration Robotics has turned to bespoke hardware to boost ROS 2: earlier this year the company launched ROBOTCORE, a hardware-agnostic acceleration framework capable of running on CPUs, GPUs, and FPGAs and delivering up to a 500-fold improvement in performance depending on the specific hardware and workload.
The microcontroller unit, dubbed roscore-v, will use a 32-bit implementation of RISC-V as a single-core in-order four-stage pipeline chip with 512kB of static RAM (SRAM), general-purpose input/output (GPIO) capabilities including four pulse-width modulation (PWM) channels, two UART, two I2C buses with an additional client, two QSPI buses, and an SDIO bus, a Fast Ethernet connection, and support for the Object Management Group's Data-Distribution Service (DDS) and Real-Time Publish-Subscribe Protocol (RTPS) interoperability standards.
The companies claim the design, which is to be released under the permissive Apache 2.0 and MIT licenses, is "silicon-proven" on nodes ranging from low-cost 130nm to low-power 22nm. The chip is also claimed to be designed with energy efficiency in mind with a power envelope measured in milliwatts, but neither company have yet released formal benchmark results to back the claim.
The companies are developing the chip as part of the ROS 2 Hardware Acceleration Working Group, initially proving the design on an FPGA before taping out silicon for potential mass production. For this, however, no deadline has yet been set.