Antmicro Releases TensorFlow Lite on RISC-V Demos Using Zephyr, LiteX, VexRiscV: TF Lite Micro
Two demos developed ahead of the RISC-V Summit taking place this week.
Antmicro has published demonstrations of TensorFlow Lite running on a RISC-V soft-core processor via the Zephyr real-time operating system (RTOS) — a port it is calling TF Lite micro — though warns that additional work needs to be done before its efforts will be reflected upstream.
"The recently released TensorFlow Lite port to Zephyr for LiteX/VexRiscv presents a proof of concept implementation of TF Lite running on a small soft CPU-based system in FPGA," Antmicro explains, referring to the LiteX soft system-on-chip solution and the VexRiscV RISC-V soft-CPU implementation. "In the TF Lite context, LiteX combines the best of both worlds — as it enables a system designer to easily create a soft CPU based SoC in FPGA and focus on the capability to extend it with custom, ML-oriented blocks."
To prove its point, the company has released two demonstrations. The first is a basic "Hello World" application, written in TensorFlow Lite, which prints sine function values to a connected serial terminal; the second is somewhat more involved, collecting data from an accelerometer input and using an on-board neural network to perform gesture recognition on-device.
"The demos present the functionality of the system and prove that TensorFlow Lite can be successfully run in Zephyr on a LiteX system with a VexRiscv CPU," the company further explains. "However, additional work needs to follow for the code to be merged upstream. While the FPGA platform definition code — done as part of our earlier efforts — has been merged some time ago, Zephyr support for TensorFlow Lite and the Zephyr driver for the accelerometer used in the demo have not yet been added upstream."
"The demos present the functionality of the system and prove that TensorFlow Lite can be successfully run in Zephyr on a LiteX system with a VexRiscv CPU," the company further explains. "However, additional work needs to follow for the code to be merged upstream. While the FPGA platform definition code — done as part of our earlier efforts — has been merged some time ago, Zephyr support for Tensorlow Lite and the Zephyr driver for the accelerometer used in the demo have not yet been added upstream."