Cadence Announces the Tensilica Xtensa LX8, Promising Better Performance and TinyML Tweaks
Eighth-generation part comes with a system performance boost of up to 50 percent, but there's no word yet on design wins.
Cadence has announced the launch of its eighth-generation Tensilica Xtensa processor platform, the Xtensa LX8 — promising new features designed to boost the performance of on-device artificial intelligence (AI) workloads and tiny machine learning (tinyML) without breaking power envelopes.
"Today’s advanced SoC designs demand even greater processor subsystem performance. Processors based on the Xtensa LX platform are widely used today in the most demanding audio/voice, automotive ADAS, and embedded computing applications, so we have extensive first-hand knowledge of our customers’ challenges in the drive for ever-increasing system-level performance," claims Cadence's David Glasco in support of the launch. "Key capabilities in the latest generation of our industry-leading extensible processor platform enable our customers to create even more advanced domain-specific processors."
The 32-bit Xtensa LX8 is based on a configurable five- or seven-stage pipeline with improved branch prediction for a performance boost, offers configurable instruction and data caches alongside flexible layer two (L2) cache memory, and has the option of adding application-specific instruction set extensions, execution units, register files, and input/output (IO) capabilities, Cadence has confirmed. It includes memory protection and management units (MPU and MMU), a 40-bit memory address space, an integrated direct memory access (DMA) controller, and a floating point unit (FPU) offering single- and double-precision operation.
According to Cadence's internal testing, the LX8 should offer a boost to system-level performance of up to 50 percent over its seventh-generation predecessor — though actual performance and capabilities will vary depending on how it's configured by the company's customers as it gets added into microcontrollers and systems-on-chips (SoCs).
On the topic of design wins and finalised specifications, there is little to report at present: while Cadence customers SK Hynix and Synaptics have spoken out in support of the core IP, neither have announced designs — and one of the biggest users of Tensilica Xtensa IP, Espressif, recently announced it would be moving away from the platform in favor of the free and open-source RISC-V architecture for all future chips.
The Tensilica Xtensa LX8 is shipping to unnamed "early access customers" now, Cadence has confirmed, with general availability expected in the late third quarter of the year. More information is available on the Cadence website.
