Clever Capacitor Constructions Let This New Receiver Chip Reject 40 Times More Interference
By combining parallel and serial capacitor networks, a novel chip design dramatically boosts its ability to handle harmonic interference.
Researchers at the Massachusetts Institute of Technology (MIT) have developed a novel chip design for mobile devices that, they say, can better reject unwanted signals — reducing interference without harming performance.
"A lot of other wideband receivers don’t do anything about [interference-causing] harmonics until it is time to see what the bits mean," lead author Soroush Araei explains of the team's work, which focused specifically on reducing the impact of harmonic interference. "They do it later in the chain, but this doesn’t work well if you have high-power signals at the harmonic frequencies. Instead, we want to remove harmonics as soon as possible to avoid losing information."
What the team has designed is a chip with a mixer-first architecture, inspired by techniques used in digital signal processors (DSPs) for block digital filtering. By adapting these techniques to analog signals, using capacitors added to the chip's design, the team was able to dramatically reduce harmonic interference — blocking interference 40 times stronger than its competitors with only a marginal reduction in the strength of the received, desired, signal.
The secret lies in how the capacitors are used, with some components arranged in parallel to share charges and others in series to form stacks. "People have used these techniques, charge sharing and capacitor stacking, separately before, but never together," Araei explains. "We found that both techniques must be done simultaneously to get this benefit. Moreover, we have found out how to do this in a passive way within the mixer without using any additional hardware while maintaining signal integrity and keeping the costs down."
"We are interested in developing electronic circuits and systems that meet the demands of 5G and future generations of wireless communication systems," says senior author Negar Reiskarimian, assistant professor, of the potential impact of the team's work. "In designing our circuits, we look for inspirations from other domains, such as digital signal processing and applied electromagnetics. We believe in circuit elegance and simplicity and try to come up with multifunctional hardware that doesn’t require additional power and chip area."
The team's work was accepted to be presented at the IEEE International Solid-State Circuits Conference (ISSCC) 2023, but was not yet publicly available at the time of writing. More information is available on MIT News.