CVA6: A Linux-Capable RISC-V CPU

RISC-V is an open source, extensible Instruction Set Architecture (ISA) that has gained a lot of popularity in the past few years. One of RISC-V's key features is that it boasts an overall architecturally neutral design with floating-point support, a load-store architecture, sign extension acceleration, and multiplexer simplification. This makes RISC-V a cost-effective option for soft processors on FPGAs. Linux-capable RISC-V CPUs have been of interest since the introduction of the RISC-V ISA, and some really great options such as CORE-V CVA6 have been popping up on GitHub.

CORE-V CVA6 is a six-stage, single issue, in-order CPU which implements the 64-bit RISC-V instruction set. The CPU implements three privilege levels (M, S, U) in order to fully support a Unix-like operating system such as Linux, and is compliant to the draft external debug spec 0.13. The goal of the CVA6 core is to run a full OS at a reasonable speed and IPC (instructions per cycle).

CORE-V CVA6, also titled the Ariane CPU, achieves this by a six-stage pipelined design (going from left to right in the above block design graphic):

PCGen stage — PC generation is a frontend stage in the pipeline responsible for generating the next program counter and communicates with the Instruction Fetch (IF) stage using a handshake signal. IF signals its readiness with an asserted ready signal while PC Gen signals a valid request by asserting a valid signal.

IF stage — The other frontend stage in the pipeline is the Instruction Fetch stage (IF), which gets its information from the PC Gen stage for branch prediction, the current program count (PC), and if the request is valid. The IF stage then requests the MMU to translate the address on the requested PC, along with controlling the instruction memory interface.

ID stage — The Instruction decode stage is the fist pipeline stage of the processor's back-end. Its extracts instructions from the data stream it gets from IF stage and decodes them, to then send them to the issue stage.

Issue stage — The Issue stage receives the decoded instructions to then issue them to the various functional units such as the ALU, CSR, LSU, multiplier, etc. The issue stage also keeps track of all issued instructions, the functional unit status, and receives the write-back data from the execute stage.

EX stage — The execute stage is a logical stage which encapsulates all the functional units (FUs) which are the ALU, Branch Unit, Load Store Unit (LSU), Multiplier, and CSR buffer. Each of these FUs in the CVA6 architecture do not have inter-unit dependencies and perform all of their operations independently of each other.

Commit stage — This is the last stage and it is responsible for taking incoming instructions to update the architectural state, managing the various exception sources, and controls the overall stalling of the processor.

Furthermore, the CPU features a scoreboard to hide latency to the data cache by issuing data-independent instructions to increase the overall IPC of the design. The L1 instruction cache has an access latency of one cycle on a hit, while accesses to the L1 data cache have a latency of three cycles on a hit.

The CORE-V CVA6 currently has a functional build running on Digilent's Genesys 2 Kintex-based FPGA development board. The Ariane CPU is connected to the peripheral of the FPGA via AXI-4 and two input interrupts. The ethernet controller is currently still in the works, so the Ariane CPU isn't quite networking capable yet, but updates are expected soon.

The OpenHW Group, who is responsible for the development of the Ariane CPU, has done a great job at providing documentation on how to get started with running user-space applications on the CPU, emulate it on an FPGA, and subsequent debugging tips.

The issues section of the repository also gets a healthy amount of attention from the developers, so this will definitely be a RISC-V soft processor option to keep in mind for current and future projects.