ETH Zurich Team Unveils RISC-V-Based Snitch Processor, Boasts of Sixfold Performance Gains

A team of computer scientists at ETH Zurich have unveiled a new RISC-V processor design dubbed Snitch, which they claim offers impressive speed — more than six times better performance and a near-fourfold gain in energy efficiency for multi-core workloads.

"Data-parallel applications, such as data analytics, machine learning, and scientific computing, are placing an ever-growing demand on floating-point operations per second on emerging systems," the team explains. "With increasing integration density, the quest for energy efficiency becomes the number one design concern."

"While dedicated accelerators provide high energy efficiency, they are over-specialized and hard to adjust to algorithmic changes. We propose an architectural concept that tackles the issues of achieving extreme energy efficiency while still maintaining high flexibility as a general-purpose compute engine."

Snitch takes a different approach. Built around the free and open-source RISC-V instruction set architecture, with two "minimally intrusive extensions," Snitch combines a small control core with a double-precision floating point unit (FPU). The first extension allows the processor to avoid many explicit memory instructions; the second allows the floating-point processor to operate without loading down the control core, allowing it to get on with other tasks.

"[These make] Snitch and FPU effectively dual-issue at a minimal incremental cost of 3.2 per cent," the team explains. "The two low overhead ISA extensions make Snitch more flexible than a contemporary vector processor lane, achieving a 2× energy-efficiency improvement."

In physical testing, having built an eight-core Snitch on a 22nm process node, the actual gains proved impressive: up to a 6.45× boost in multi-core performance and a 3.5× gain in energy efficiency.

Speaking to IEEE Spectrum, first author Florian Zaruba admitted that Snitch is more complicated to program than other accelerators — but is also more versatile, and considerably more energy-efficient. Zaruba also teased "exciting opportunities ahead" to scale the project to "thousands of Snitch cores, even spreading over multiple chiplets."

The team's work has been published in the journal IEEE Transactions on Computers under closed-access terms, with an open-access version available on arXiv.org. Source code for the design, meanwhile, has been published on the PULP Platform GitHub repository under the permissive Apache 2.0 license.