Europe Picks RISC-V to Power Future AI Supercomputers, Launches the DARE Project
"Digital Autonomy with RISC-V in Europe" seeks to reduce the region's reliance on foreign technologies, building atop the RISC-V ISA.
Europe has announced a project that aims to deliver native technology for high-performance computing (HPC) and artificial intelligence (AI) — funding the development of supercomputing hardware and supporting software, based on the free and open source RISC-V instruction set architecture.
"I am proud to announce the launch of the DARE project, which marks a significant milestone for European digital sovereignty," says Anders Jensen, executive director of the EuroHPC Joint Undertaking (JU) supporting the new project. "This ambitious initiative will drive innovation in both hardware and software technologies and leverage the full power of HPC and AI to develop secure, efficient, and European-led solutions for the future."
DARE SGA1, the Digital Autonomy with RISC-V in Europe Special Grant Agreement 1, marks a three-year project as part of a larger six-year effort to minimize European dependence on foreign technology by creating its own processors and supporting hardware and software for a native supercomputing system. The heart of the effort: the free and open source RISC-V architecture, on which anyone can build direct or derivative devices without having to sign non-disclosure agreements or pay licensing fees.
"DARE is daring to start from the top of the technological complexity pile and produce European-designed processor chips for supercomputers," claims DARE SGA1 principal investigator Osman Unsal of the project, "paving the way for Europe's digital sovereignty."
The initial three-year effort will focus on the development of three RISC-V-based "chiplet" designs that can be combined into a single physical processor: a vector accelerator, the development of which will be led by Openchip; an accelerator for artificial intelligence inference workloads, led by Axelera AI; and a general-purpose processor built with a focus on high-performance computing workloads, led by Codasip. All three will target "advanced CMOS technology nodes," the team has said.
The hardware will be designed alongside supporting software, with the two being worked on hand-in-hand as part of a co-design approach. RISC-V emulators and simulators will support the software development until the hardware is ready, and the project will include "exploratory pathfinding [software and hardware] design activities," its team says.
More information on the DARE project, which has a first-phase budget of €240 million (around $261 million), is available on the official website.
