Microchip Unveils the High-Performance Eight-Core RISC-V PIC64HX Processor Family

Microchip has announced the latest entry in its 64-bit microprocessor range, the RISC-V-based eight-core PIC64HX family — which launches with on-board acceleration for artificial intelligence and machine learning (AI and ML) workloads and "post-quantum security" features.

"The PIC64HX MPU [Microprocessor Unit] is truly groundbreaking in the number of advanced features we are able to provide with a single solution," boasts Microchip's Maher Fahmi of the company's latest part. "And, integrating TSN [Time-Sensitive Networking] Ethernet switching into the MPU helps developers bring standards-based networking connectivity and compute together to simplify system designs, reduce system costs, and accelerate time to market."

The integrated 240Gb/s TSN-enabled Ethernet switch is far from the chips' only feature: the PIC64HX has no fewer than eight 64-bit SiFive Intelligence X280 RISC-V cores, configurable for symmetric or asymmetric multiprocessing (SMP or AMP) or dual-core lockstep mode, running at up to 1GHz. Vector extensions are included, to deliver the promised acceleration for on-device edge AI and ML workloads, and there's hardware virtualization functionality too.

Microchip isn't just planning to cover current industry needs, though, but is also looking to the future: the parts are among the first on the market to come with support for the NIST FIPS 203 (ML-KEM) and FIPS 204 (ML-DSA) algorithms — designed to provide protection against as-yet theoretical attacks by large-scale quantum computers yet to be developed. The chips also include WorldGuard, a security feature delivering hardware-based spatial and temporal partitioning — allowing for up to 32 domains at once.

The chips come with two DDR memory interfaces supporting up to 32GB of DDR4-3200 per interface, supports eMMC, SD Card, NAND and NOR flash, static RAM (SRAM), and magnetoresistive RAM (MRAM) for non-volatile storage, has up to two PCI Express Gen. 3 eight-lane or four PCIe Gen. 3 four-lane ports, Compute Express Link (CXL) 2.0 connectivity, up to two USB 3.0 ports, two SPI, four UART, four I2C, two MDIO buses, and 64 general-purpose input/output (GPIO) pins — plus JTAG debugging.

The parts are due to sample with "early access partners" in early 2025, Microchip has confirmed — with no word yet on pricing or general availability for the chips, which will launch in -IN, -AV, and -MI suffixed variants for industrial, aviation, and military use respectively. More information is available on the official product page.