MicroZed Chronicles: XDF and VITIS

Since the announcement of the Versal ACAP at XDF18, there has been great interest in the software environment which developers will use to leverage Versal ACAP and its vast capabilities.

Yesterday in the keynote at XDF19, it was announced the new unified software environment would be called Vitis and most exciting of all it would be available from the end of the month be heavily open source based and free.

Fortuitously, when I registered which sessions I wanted to attend at XDF, I had selected most of the unified software environment talks. So in the reminder of this blog we will take a look at the important Vitis details.

The first thing to point out is the Vitis is not limited to only ACAP development it is also supports exiting Zynq, MPSoC and RFSoC devices as well. Meaning, we can start leveraging its development advantages in our existing developments.

Vitis is a unified software environment for all Xilinx platforms, which means we can use Vitis to develop applications for Alveo Accelerator cards, embedded platforms or FPGA in the cloud. Changing the target requires only changes to the make file.

To achieve this, Vitis uses a stack based architecture across four layers:

• Vitis AI - Domain specific architectures enabling TensorFlow and Caffe frameworks to be optimized, compressed and compiled to run on a Xilinx devices in minutes.
• Vitis Accelerated Libraries - Several hardware accelerated libraries including video, image processing, AI, fintech and security.
• Vitis Core - Includes the Xilinx Runtime library, compilers, debuggers and analyzers.
• Vitis Base - Platform definition of the hardware including IO abstraction.

One of the key elements of Vitis is the Xilinx Runtime (XRT), this is the same XRT which has been used for several years as part of the PCIe based accelerators like the Alveo boards.

XRT is combination of a runtime software layer and kernel driver that allows software to interact with programmable logic and Versal accelerators.

The development flow in Vitis is clearly defined for hardware and software:

• Hardware development flow uses C or C++ and high level compilers - the actual contents of the accelerator is determined by the SW calling hardware optimized libraries, RTL functions or translation into hardware directly. System composition and connectivity are defined by command lines
• Software development flow is identical to a standard software build.

In a change from previous tools, Vitis is designed to plug in directly with popular open source development and build tools.

To get going with the new tool, Xilinx have launched a developer area at https://developer.xilinx.com. Here, you can find 30 articles and documents across a range of applications showing how we can leverage Vitis.

It goes without saying that once Vitis is available, we will be heavily focusing on it in the blog as we explore how we can use to accelerate out Zynq, MPSoC and eventually Versal designs. Until then, stay tuned!

See My FPGA / SoC Projects: Adam Taylor on Hackster.io

Get the Code: ATaylorCEngFIET (Adam Taylor)

Access the MicroZed Chronicles Archives with over 300 articles on the FPGA / Zynq / Zynq MpSoC updated weekly at MicroZed Chronicles.