NXP Unveils the i.MX 95 System-on-Chip Family, Promising Security, Safety, and On-Board ML Engines

NXP Semiconductors has announced a new range of application-class processors in the i.MX family, the i.MX 95 — aiming to deliver, the company claims, "safe, secure, and scalable AI" at the edge.

"The i.MX 95 family brings unparalleled features and performance to markets like automotive and industrial where security and safety are key," says NXP's Rafael Sotomayor of the company's latest application processor range. "The i.MX 95 brings together NXP eIQ Neutron NPU [Neural Processing Unit], Arm Mali graphics, integrated heterogeneous safety domain, and networking capabilities to create a truly unique solution. Combining our deep expertise in functional safety with AI acceleration, high performance CPU cores, and high-throughput connectivity, NXP is creating the standard for a new generation of safe and secure edge platforms."

At the heart of the i.MX 95 is an up-to-six-core Arm Cortex-A55 processor cluster with floating-point unit and NEON acceleration, supported by a real-time Arm Cortex-M7 microcontroller with floating-point unit, nested vector interrupt controller (NVIC), and memory protection unit (MPU.) Alongside these is what NXP calls the "low-power real-time domain," which includes system control hardware, connectivity, and another processor — this time an Arm Cortex-M33 dedicated to safety tasks. They're joined by an EdgeLock secure enclave, which includes everything from a true hardware random number generator and cryptographic hardware to tamper detection capabilities and a secure clock.

For on-device machine learning workloads, the i.MX 95 includes NXP's eIQ Neutron neural processing unit (NPU) accelerator. Designed to support "most neural network types" including convolutional neural networks (CNNs), recurrent neural networks (RNNs), temporal convolutional networks (TCNs), and transformers, the accelerator supports an image signal processor (ISP) optimized for machine vision applications — including high dynamic range (HDR) support from two exposures, de-noising and edge enhancement algorithms, and support for two regions of interest.

For connectivity, the chip includes I2C, I3C, UART, USART, SPI, and CAN-FD buses, includes two MIPI CSI four-lane and one MIPI DSI four-lane connections for cameras and displays, one eight-lane LVDS video output that can be split into two four-lane outputs, two gigabit Ethernet and one 10-gig-Ethernet connections all with time-sensitive networking (TSN) support, USB 3.0 and USB 2.0, two PCI Express Gen 3.0 lanes, an eight-channel microphone input, and support for LPDDR5 or LPDDR4X external memory.

NXP's segmented design has a key purpose: using the company's "Energy Flex" architecture, it's possible to enable and disable various sections of the chip independently, including turning off the application-class processors entirely while leaving the real-time safety domain running and active. That's key for the markets NXP is hoping to hit with its latest chips: automotive and industrial, where safety and security are key, plus the Internet of Things.

The company has confirmed plans to launch "multiple options" in the i.MX 95 family, with varying specifications and power requirements, with sampling due to begin for "lead customers" in the second half of the year. More information is available on the NXP website.