Papon Charles' NaxRiscV Offers a Fully-Open, Linux-Capable RISC-V System-on-Chip Design for All

Hardware engineer Papon Charles has put together a free and open source system-on-chip design, built around the RISC-V instruction set architecture, capable of booting into the RISC-V port of Debian Linux: NaxRiscv.

"[There weren't] many OoO [Out-of-Order] open source soft-cores out there in the wild (Marocchino, RSD, OPA…)," Charles explains of his decision to develop NaxRiscv, an out-of-order superscalar RISC-V core. "The bet was that it was possible to do better in some metrics, and hopefully being good enough to justify in some project the replacement of single-issue/in-order core soft-cores by providing better performance (at the cost of [silicon] area)."

The free and open source RISC-V instruction set architecture has already made impressive inroads in the embedded field as an alternative to proprietary microcontroller architectures, and devices like the upcoming StarFive VisionFive 2 show that it is ready to take on application-class devices too — but the majority of these commercial implementations use closed-source cores. NaxRiscv, by contrast, is fully open — and thanks to its integration into LiteX, can now be used to instantiate a fully-functional Linux-capable RISC-V system-on-chip on affordable FPGA hardware.

"[This is] RISC-V 64-bit Debian on [a Digilent] Genesys 2 [FPGA development board] with fully open source SoC," open development specialist Enjoy Digital writes in a message accompanying demonstration images. "[Papon Charles'] NaxRiscv 64-bit CPU integrated with LiteX (LiteDRAM DDR3 + LiteSDCard + 1Gbps LiteEth + Framebuffer + base peripherals). What a relief to just be able 'apt install' packages."

Those who want to try the SoC for themselves can find full instructions in the NaxRiscv documentation; the source code for NaxRiscv is available on GitHub under the permissive MIT license.