Pragmatic, Harvard, and Qamcom Build the World's First Silicon-Free Flexible RISC-V Microcontroller

Flexible integrated circuit (IC) specialist Pragmatic has unveiled its latest fully-functional plastic processor, a bendable 32-bit RISC-V chip that works even when curled up — and is capable of running on-device machine learning and artificial intelligence (ML and AI) workloads.

"This is an exciting step forward in flexible semiconductor technology. Enabling an open-standard, non-silicon 32-bit microprocessor will democratize access to computing, unlocking emerging applications while opening the door to sub-dollar compute," claims Pragmatic's lead researcher and senior director of processor development Emre Ozer. "By enabling scalable, low-cost compute in a flexible form factor — in combination with the rapid turnaround and low non-recurring engineering costs associated with our FlexIC Foundry — we really are ushering in a step-change in the art of the possible for flexible electronic systems."

Pragmatic's promise is to take the brittle, inflexible silicon out of electronic chips and replace it with softer semiconductors on a plastic substrate. The result: working chips that can be rolled, bent, and in some cases even folded. In this case, that chip is the company's most complex yet: an implementation of the free and open source RV32E RISC-V instruction set architecture, dubbed Flex-RV — built using indium gallium zinc oxide (IGZo) thin-film transistors on a polyimide substrate.

This isn't Pragmatic's first flexible processor: three years ago the company built a bendy reimplementation of the MOS Technology 6502, a vintage eight-bit microprocessor known for its presence in market-defining devices including Apple's early computers and the Commodore 64 — then partnered with Imec to develop a commercialized version targeting ultra-low-power Internet of Things (IoT) devices. The same technology has also been used to develop fully flexible displays, in partnership with Ynvisible.

The prototype proof-of-concept device, built in partnership with researchers at Harvard University and Qamcom, proved capable of running microcontroller workloads — including tinyML tasks, boosted by an internal hardware accelerator separate to the RISC-V core — while both flat and tightly bent, in the latter case only dropping around 4.3 per cent performance. The catch: while low power, at just 6mW under load, the chip was only tested at a somewhat sedate clock speed of just 60kHz — or 0.06MHz.

The project is detailed in full in a paper published in the journal Nature, under open-access terms, for which Ozer is the first and corresponding author.