Renesas Shows Off a High-Performance STT-MRAM Design for 200MHz-Plus Microcontrollers
Offering read and write speeds eclipsing previous efforts, MRAM could be coming to a microcontroller near you sooner thank you think.
Renesas has announced the creation of a spin-transfer torque magnetoresistive random-access memory (STT-MRAM) test chip that, it says, offers high performance for both read and writes — offering a real alternative to traditional flash chips for performance-sensitive microcontrollers.
"As IoT [Internet of Things] and AI [Artificial Intelligence] technologies continue to advance, MCUs [Microcontroller Units] used in endpoint devices are expected to deliver higher performance than ever," Renesas says of its work on the memory technology. "The CPU clock frequencies of high performance MCUs are in the hundreds of megahertz, so to achieve greater performance, read speeds of embedded non-volatile memory need to be increased to minimize the gap between them and CPU clock frequencies."
Spin-transfer torque magnetoresistive random-access memory (STT-MRAM), more commonly just called MRAM, aims to bridge the gap between non-volatile but relatively slow flash memory and volatile but fast dynamic and static RAM (SRAM and DRAM) by using spin-based magnetic storage rather than electric charge or the flow of current. While write speeds have proven high, though, read operations have traditionally lagged — which is where Renesas' work comes in.
The test chip developed by the company uses two new mechanisms for improved read speed: aligning the reference current for a given chip to the center of the cells' distribution based on real-world tests, and reducing the offset of the sense amplifier. Coupled with a new connection approach, the chip offers what Renesas says is the "world's fastest random read access time" at 4.2ns — meaning it can operate at frequencies of 200MHz and beyond.
At the same time Renesas has given the chip a write-performance boost using technology it originally developed in December 2021, tweaked to use a higher step-down voltage from input to output to increase performance by another 80 per cent — resulting in a test chip writeable at a sustained 10.4MB/s. Finally, the company added 0.3Mb of one-time programmable (OTP) memory based on MRAM memory cell breakdown technology, which it says can be written in-the-field when required.
Renesas presented its work at the International Solid-State Circuits Conference 2024 (ISSCC 2024), but has not yet offered a timescale for commercialization.