RVAM16 Promises Performant Arm Thumb Translation on Low-Power RISC-V Microcontrollers
Resource-light hardware binary translation approach delivers the ability to run Arm binaries at up to 65 percent of their original speed.
Researchers from China's National University of Defense Technology have proposed a new hardware binary translation microarchitecture that is designed to bridge the gap between proprietary Arm and free and open source RISC-V parts: RVAM16.
"Integrating multiple ISAs through hardware-based translation allows embedded systems to evolve without the high cost of rewriting software," explains corresponding author Yhanhu Cheng of the team's work, which aims to allow programs written and compiled for Arm-architecture chips to run on RISC-V devices with as close to native performance as possible.
Arm, originally Acorn RISC Machine and later Advanced RISC Machines, launched in 1985 as a spin-off from Cambridge-based Acorn Computers. The original ARM1 chip was designed as a coprocessor for the BBC Micro home computer, with subsequent designs powering Acorn's Archimedes and RiscPC families. Today, it's one of the most broadly-deployed families of processor architecture around — but has recently received competition from RISC-V, a free and open source architecture which allows anyone to design their own chips without signing contracts or paying a licensing fee.
As with historical shifts in architecture — most notably Apple's repeated moves from the MOS 6502 to the Motorola 68000 to PowerPC to Intel to Arm — there's one major problem: software support. Binaries compiled for one architecture aren't compatible with other architectures, and while software compatibility layers are possible they're resource-intensive and sap performance.
RVAM16 tries to solve that with a binary compatibility layer implemented in hardware, with a specific focus on microcontrollers and other resource-constrained implementations. The microarchitecture takes in binaries compiled for Arm Thumb and translates their instructions to RISC-V equivalents automatically — providing compatibility without the performance penalties associated with doing the same in software.
In test, RVAM16 was found to run Arm Thumb binaries at up to 65 percent of their original speed — which is almost six times faster than traditional software-based translation approaches. The researchers also point to the design's minimal hardware requirements, claiming that it can be applied to ultra-low-power chips for wearables like smartwatches, medical sensors, and battery-powered industrial monitoring and automation systems.
The team's research has been published in the journal Frontiers of Computer Science under closed-access terms.
