RVSoC Offers a Lightweight Linux-Capable RISC-V Core in Just 5,000 Lines of Verilog

A team from the School of Computing at the Tokyo Institute of Technology has developed a portable and Linux-capable RISC-V system-on-chip (SoC) design in just 5,000 lines of Verilog — and pledges to release it to all.

"RISC-V is an open and royalty free instruction set architecture which has been developed at the University of California, Berkeley. The processors using RISC-V can be designed and released freely," the team explains by way of background. "Because of this, various processor cores and system on chips (SoCs) have been released so far. However, there are a few public RISC-V computer systems that are portable and can boot Linux operating systems.

"In this paper, we describe a portable and Linux capable RISC-V computer system targeting FPGAs in Verilog HDL [Hardware Description Language]. This system can be implemented on an FPGA with fewer hardware resources, and can be implemented on low cost FPGAs or customised by introducing an accelerator."

The resulting design, dubbed RVSoC, implements the 32-bit RV32IMAC instruction set architecture and offers a 12-stage pipeline with a memory management unit (MMU) - not strictly required for booting Linux, given the kernel's support for manual memory mapping in the event of no hardware MMU being available, but definitely a nice-to-have for all but the most basic of possible uses. Despite this, the design comes in at a mere 5,000 lines of Verilog HDL.

"We are planning to release the RTL code of the designed RVSoC as an open and royalty free RTL design," the team pledges. "Because RVSoC is a computer system that supports Linux and uses a small amount of hardware resources, it can be applied to various purposes. A feature of RISC-V is that it has a room for the extended instructions by computer system developers. The ability of extension can be the basic requirement for application-specific accelerators and it enables to implement more specialised instruction sets.

"The resource-saving of RVSoC can be suitable for the implementation of various accelerators and special processor cores by adding unique instructions, and the development of related software.The number of lines in Verilog HDL code of RVSoC is about 5,000, and it is relatively easy to understand the entire implementation of the Linux capable computer system. Therefore, it is suitable to be used as a sample computer system of the education on computer science."

A preprint of the paper, which is to be published in the journal IEICE Transactions on Information and Systems, is available through arXiv.org. Additional information can be found on the project homepage.