SiFive Targets Energy-Efficient AI with Its 16 TOPS RISC-V Intelligence XM Series Clusters

RISC-V pioneer SiFive has announced the Intelligence XM Series, processor cores targeting high-performance artificial intelligence (AI) and machine learning (ML) workloads — and it's promising to open source its in-house kernel library to speed development.

"Many companies are seeing the benefits of an open processor standard while they race to keep up with the rapid pace of change with AI. AI plays to SiFive's strengths with performance per watt and our unique ability to help customers customize their solutions," claims SiFive chief executive officer Patrick Little of the company's new core design. "We're already supplying our RISC-V solutions to five of the 'Magnificent 7' companies, and as companies pivot to a 'software first' design strategy we are working on new AI solutions with a wide variety of companies from automotive to datacenter and the intelligent edge and IoT [Internet of Things]."

SiFive was an early adopter of the free and open source RISC-V instruction set architecture, designing a range of processor IPs from microcontrollers up to server-class application processors. Some it made in-house and launched in hardware products including the Arduino UNO-like HiFive1 and ITX-format HiFive Unmatched — and its most recent product, the HiFive Premier P550, which targeted on-device machine learning and artificial intelligence workloads.

Other designs it offers as licensable IP for others to build into their products, in much the same way as rival Arm. The Intelligence XM Series is, at the time of writing, in the latter camp: a licensable IP that provides RISC-V-based X-Cores in a cluster configuration claimed to offer 16 tera-operations per second (TOPS) of INT8-precision compute or eight tera-floating point operations per second (TFLOPS) at BF16 precision, with 1TBs of sustained memory bandwidth.

While SiFive is positioning the Intelligence XM Series as a dedicated AI accelerator, it can also be the only CPU in a system: the company says it expects customers to build devices "incorporating no host CPU," though they can also use the cores as coprocessors for RISC-V, x86, or Arm cores.

"RISC-V was originally developed to efficiently support specialized computing engines including mixed-precision operations," claims SiFive founder and chief architect Krste Asanovic of its suitability for the task. "This, coupled with the inclusion of efficient vector instructions and the support of specialized AI extensions, are the reasons why many of the largest datacenter companies have already adopted RISC-V AI accelerators."

More information on the SiFive Intelligence XM Series is available on the company's website; SiFive has also promised to release its kernel library under an unspecified open source license "to speed up development time," though at the time of writing had not committed to a timescale for general availability.