Digital clock (time watch) on 4 single 7 segment common anode display implemented hardware on Xilinx Spartan 6 FPGA. Use.ucf (implementation constrains) file to assign user IO ports of FPGA to Inputs & Outputs of.vhd (VHDL) file.
Ninad Waingankar
10 projects • 19 followers
Embedded Systems
Microcontrollers
Microprocessors
VLSI Designer
FPGA Designer
IOT
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