This project presents and provides the open-source Pixblasters-Light-APA102 FPGA LED controller. It enables big and affordable handmade video LED displays that connect to any computer as the standard monitor and displays any video content with absolutely no programming required.
LED displays can be quickly built by very cost-effective RGB LED strips to provide the best of the high-end professional solutions such as size, content management and visibility. Such displays can be curved and glued to different surfaces in big video installations that cannot be supported by standard rigid LED modules.
Here presented open-source VHDL code, originally designed for Xilinx FPGAs, provides the complete logic controls for huge, i.e. 0.5 wide and 15 meters long LED displays. For example, such displays would be able to continuously show the latest news picked from the Internet by the RSS News Ticker application running on an old PC. Colors, fonts, or even inserted full-color commercials, can be easily controlled through the available off-the-shelf software.
Video 1 shows a small APA102 LED (actually built by compatible SK9822 LEDs) display model running the RSS news feed. While the PC runs the Desktop Ticker* application, the FPGA LED controller works as a second monitor, cuts out a defined portion of the screen and displays any video content from that image window.
The Pixblasters-Light-APA102 is a test version of the final APA102 (4-wire) LED controller that will be integrated in the official Pixblasters MS1 Video Led Controller’s firmware. Find more at www.pixblasters.com.
If you are interested in driving 3-wire LEDs, such as WS2812B and similar, please check our older post: https://www.hackster.io/pixigreen/convert-a-bunch-of-led-strips-into-a-big-video-display-c90380
* We thank Mr. Mike Batt from http://www.battware.co.uk for the permission to use the Desktop Ticker application in this demo.
APA102 Protocol ExplainedAPA102 LEDs can be controlled through the standard 4-wire LED interface that consists of the DATA/CLOCK pair, power and ground lines. The separated clock line makes the APA102 LEDs less timing sensitive than 3-wire LEDs, such as the WS2812B LED with the clock embedded within the data signal. This feature makes them very popular among software developers and enables control of reasonable number of LEDs within multitasking operating system. However, applications with thousands of LEDs should be controlled by customized hardware peripherals – such as the Pixblasters MS1 Video LED Controller.
Figure 1 explains the APA102 interface.
The Pixblasters-Light-APA102 FPGA controller follows the control sequence shown in Figure 1. There are sixteen (16) channels for a parallel control of up to 512 RGB LEDs in each line (channel). The following figures show how the LED interface looks in reality.
Figure 2 shows the beginning of the display line. The blue oscilloscope line marks the Start of Frame and you can see the yellow DATA line fixed to 0 during that period of time. The first pixel starts immediately after the Start of Frame with the fixed three (3) leading 1s and the 5-bit brightness forced to the maximum. Idling between subsequent pixel data is not necessary.
Figure 3 shows one pixel shifted out from the controller towards LEDs. The blue line marks beginning of two subsequent pixels. Note the pixel’s beginning of eight (8) 1s, three fixed lead 1s followed by the 5-bit maximum brightness value (like in Figure 2). Than the RGB value 0x030200 is shifted out. LEDs sample input data on the rising clock edge.
APA102 LEDs connected in the shift chain require additional 1s to be shifted as the End of Frame sequence. The probable explanation is that the data for each subsequent LED delays by half a clock cycle, while the clock is not. Therefore, additional clock cycles have to be fed to the chain even after all data has been sent.
Figure 4 shows the end of the line shift – the End of Frame that lasts seventeen (17) pixel periods: 17 x 32 = 544 clock periods. The oscillogram was taken during code testing and shows an atypical use case. The blue line marks beginning of each new pixel period, while the pink line is the clock signal. For the pixel line of max 512 LEDs, the End of Frame does not have to be longer than 256 clock periods.
Build and Operate APA102 LED DisplayThe following parts are needed to support the RSS News Ticker and other video demos:
- APA102 LED matrix
- FPGA LED controller
- Video source that can be PC, Raspberry Pi, or any other computer with the standard monitor output
The following video clip shows the buildup of the demo display running the RSS News Ticker.
To learn more on how the Pixblasters-Light LED controllers work, how to power up the display, how to implement the VHDL code and how to use it on non-Pixblasters hardware platforms, please visit our previous post: https://www.hackster.io/pixigreen/convert-a-bunch-of-led-strips-into-a-big-video-display-c90380
The Pixblasters-Light-APA102 is a key IP core in this project. It captures video from the DVI video input and buffers up to 16 of max 512 pixels long video lines. The IP core crops the input video at an arbitrary position, double-buffers the cropped image and shifts it out serialized in accordance to the APA102 LED interface format. The key features:
- LED capacity - 8192 RGB APA102, HD107S, SK9822 and compatible LEDs
- Max. LED display's resolution is 512 x 16 (H x V)
- Supports 60 fps vertical refresh
- RGB888 pixel format - 16M full colors
- Integrated RGB LED gamma color correction
- Crops the input video and shows the selection on LEDs
- The top left coordinate of the cropping window: TOP_LEFT_X & TOP_LEFT_Y generics
- The length of the LED display line set by the LINE_LENGTH generic
- LED brightness set by the BRIGHT generic
- End of Frame length defined by the TRAILER generic
- The clock period set by the input clock and the DIVIDE_CLK generic
- Reference design for the Pixblasters MS1 board supports 24 MHz, 12 MHz, 6 MHz and 3 MHz LED clock
FPGA implementation instructions:
- Download the FPGA code from Pixblasters github repository: https://github.com/PixiGreen/Pixblasters-MicroDemo-APA102
- Make sure to have installed the Xilinx ISE WebPack. This free and the fully featured front-to-back solution is available for download: https://www.xilinx.com/products/design-tools/ise-design-suite/ise-webpack.html
- Follow step-by-step implementation instructions provided in the readme.md file
- Optionally, use the pre-compiled pixblasters-top.bit to configure the Pixblasters MS1 board with no design implementation
Check out the above 2-min video clip showing various demos on the nanosized APA102 LED display as well as demos on a bit bigger, mini size Pixblasters demo built by RGB LED strips. The bigger display contains 14, 400 LEDs and measures noticeable 2 x 2 meters. Full-featured Pixblasters MS1 Video LED Controllers can drive much, much bigger LED displays built of hundreds of thousands of RGB LEDs.
Here provided open-source VHDL code enables 512 x 16 (H x V resolution) LED displays. Figure 5 illustrates possible displays’ sizing. With 30 LEDs/meter strips, the length of the display can be around 17 meters:
Length = (100 cm / 30 NoLEDs) * MaxPixelNo = 3.33 cm * 512 ~ 17 m
The nano size LED display from the Video 1 actually shows all control electronics needed for displays of such enormous size. Of course, the power supply must be carefully designed. Due to tiny power lines and the number of LEDs, the 5 VDC LED strips encounter significant voltage drop causing noticeable LED dimming after a couple of meters. To overcome the dimming problem, we recommend powering the LED strip in segments, i.e. after 2 meters cut the power and ground line, and connect them directly to the power supply. LED strips with 12 VDC power supply are less prone to this problem.
Follow us to learn more about LED dimming, display construction and other LED related info - www.pixblasters.com
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