Fully pipelined implementation of FFT with fixed-point arithmetic in Vitis HLS
Implementation of fully pipelined DDS IP cores in Vitis HLS with truncated, dithered phase and Taylor serial output correction
Overview of the basic properties and characteristics as well as a detailed description of the internal components.
Implementation of Cell-Averaging (CA) and Ordered-Statistic (OS) Constant False Alarm Rate (CFAR) detector using Vitis HLS
Time and frequency domain implementation of fully pipelined Matched Filter IP core in Vitis HLS
