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3 fpga projects

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Vitis-AI DPU-TRD for 2024.x with VIVADO and Kria/MPSoC

This article is on general steps and methods for creating the Vitis AI enablement project with DPU design in 2024.x tool for Kria or MPSoC.

Vitis-AI DPU-TRD for 2024.x with VIVADO and Kria/MPSoC

LogicTronix [FPGA Design + Machine Learning Company]
135
Vitis AI 3.5 with Petalinux 2024.2

Enabling Vitis AI 3.5 and DPU in Petalinux 2024.2 for AI/ML acceleration for Kria/MPSoC/Versal.

Vitis AI 3.5 with Petalinux 2024.2

LogicTronix [FPGA Design + Machine Learning Company]
439
Titanium Ti180 FPGA ISP - Getting Started

Getting Started with Infinite-ISP, the open source image signal processor on Efinix Titanium Ti180 J484 Development kit.

Titanium Ti180 FPGA ISP - Getting Started

Muhammad Abdullah
300
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