Rajeev Patwari

1 Project5 Followers2 Following
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Bio

Engineer, Developer, Domain Specific Architectures on FPGA/ACAP for mathematical problems

Joined

November 2018

Skills

FPGA, RTL, Verilog, Python, Digital Signal Processing, Scientific Computng, C, Programming, Algorithms

Projects
Demonstrating the scientific computational power of the small ZU3EG SoC by using 8 parallel floating point accelerators running at 200 MHz.
Ultra96 FPGA-Accelerated Parallel N-Particle Gravity Sim
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AWS EC2
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Ultra96-V1
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