Hi there,
Vivado - Zynq7 & Watch Module design (feat. AXI custom IP)
Vitis
Launch & Debug
Read moreThis is a example project.
I'm trying to study HW Verilog language.
I will make a watch and this will be my first step in studying Verilog.
Block diagram & Timing graph1 ) counter.v
Block diagram
Timing graph
Vivado simulation - 1
Vivado simulation - 2
2 ) watch_top.v
Block diagram
Timing graph
Vivado simulation - Reset
Vivado simulation - 00:59:59 -> 01:00:00
Vivado simulation - 23:59:59 -> 00:00:00
Vivado diagram design
Read & Write Addr Map
ILA AXI Read Debug - Addr(0), Data(271 -> 272)
※ fatal error: xparameters.h: No such file or directory
This error is caused by the failure to create "Makefile" during the build process of Custom IP. We need to copy the Makefile contents in the default IP (e.g., 'qspips v3_10', 'gpiops_v3_11',...) and overwrite it in the Custom IP Makefile.
Comments
Please log in or sign up to comment.